DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 03/20/2026 have been fully considered but they are either not persuasive or moot in view of the indication of allowable subjected matter in light of Applicant’s amendments as detailed later.
Applicant argues on page 18 that Kondo teaches in paragraph [0022] that the coupling-region field plate and the active trench field plate are formed with substantially the same height and therefore teaches away. This is not persuasive since 1) Kondo’s paragraph [0022] discusses a different portion of the device which was not identified in the previous office action as either the first or second coupling trench regions, and 2) the entirety of paragraph [0022] clarifies that the height is not set as high as the upper surfaces of the gate electrode such that upper parts of the trenches are buried with the insulating layer, and that feature of being buried within the insulating layer is maintained in the combination of Kondo in view of Marchant.
To expand on the first point, Kondo was relied upon in e.g. FIG. 1 for teaching an intersecting trench region (154, ¶ [0017]), a first coupling trench region (one of 152 near the 101 first active region, ¶ [0017]), and a second coupling trench region (adjacent 152, ¶ [0017]). Paragraph [0022] discusses the height of field plate 136 within trench 102 which is a different region and a region closer to the middle active portion of the device rather than the terminal coupling trenches.
To expand on the second point, paragraph [0022] of Kondo states:
[0022] Here, only the field plate 136 is provided inside the trench 102 and no gate electrode is provided therein. A height of an upper surface of the field plate 136 inside the trench 102 without the provision of the gate electrode is set substantially equal to a height of an upper surface of the field plate 135 inside each trench 101 in the active region. Meanwhile, a height of an upper surface of a field plate 147 inside the trench 153 on the outer side of the target mesa portion 103 is substantially equal to the height of the upper surface of the field plate 135 inside the trench 101 in the active region. In other words, the heights of the upper surfaces of the field plates 136 and 147 inside the trench 102 without the provision of the gate electrode and inside the trench 153 on the outer side are not set as high as the height of the upper surface of the gate electrode. Instead, upper parts of these trenches are buried with the insulating layer. In this way, densification of electric field distribution in the vicinity of a side wall of the trench 102 is relaxed and an electric field of a breakdown point located at a lower part of the trench 102 is relaxed as well. Thus, the withstand voltage of the semiconductor device can be increased. [emphasis added]
Assuming for the sake of argument that Kondo intended for the teachings of paragraph [0022] to apply to also the trenches 152, Marchant also sets the height of the electrode 132 to be buried with an insulating layer 224, and therefore the teachings of Marchant are consistent with the teachings of Kondo and one having ordinary skill in the art would not have found the teachings of Marchant to teach away from Kondo.
Applicant argues on page 18 that “Marchant relates to an unrelated gate-runner structure addressing different problems” which is not persuasive as both relate to terminal electrode structures, the teachings of Marchant relate generally to trench structures, and one having ordinary skill in the art would not find the teachings of Marchant to be limited to only gate runners.
Applicant argues on page 18 that Marchant solves a different problem than Applicant which is acknowledged but moot in view of the express teachings of Marchant.
Applicant argues on page 18 that reliance on Marchant is hindsight bias which is not persuasive in view of the express teachings of Marchant.
Therefore, Applicant’s arguments with respect to claims 1 and 17 are not persuasive and the rejection maintained as detailed below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2,17-18 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2022/0223729 A1 to Kondo, “Kondo”, in view of U.S. Patent Application Publication Number 2007/0155104 A1 to Marchant et al., “Marchant”.
Regarding claims 1 and 17, Kondo discloses a semiconductor device (FIG. 1-7) and method of making thereof, comprising:
a region (drift region 113, ¶ [0018]) of semiconductor material;
a first active trench region (one or more of 101, ¶ [0017],[0018]) extending inward into the region of semiconductor material and comprising an active shield electrode (135, ¶ [0018]) in the first active trench region and separated from the region of semiconductor material by an active shield electrode dielectric (133, ¶ [0018]);
a second active trench region (adjacent 101, ¶ [0017],[0018]) extending inward into the region of semiconductor material, laterally spaced apart from and parallel to the first active trench region, and comprising the active shield electrode (135) in the second active trench region and separated from the region of semiconductor material by the active shield electrode dielectric (133);
an intersecting trench region (154, ¶ [0017]) extending inward into the region of semiconductor material and perpendicular to the first active trench region and the second active trench region;
a first coupling trench region (one of 152 near the 101 first active region, ¶ [0017]) coupling the first active trench region to the intersecting trench region and comprising a coupling shield electrode (141, ¶ [0018]) within the first coupling trench region and separated from the region of semiconductor material by a coupling shield electrode dielectric (133 in 154, “the insulating layer 133 provided in the outer peripheral trench 154, ¶ [0018]); and
a second coupling trench region (adjacent 152, ¶ [0017]) coupling the second active trench region to the intersecting trench region and comprising the coupling shield electrode within the second coupling trench region and separated from the region of semiconductor material by the coupling shield electrode dielectric (133 in 154, “the insulating layer 133 provided in the outer peripheral trench 154, ¶ [0018]);
wherein: the active shield electrode comprises a first thickness (height, see Examiner-annotated figure below) in a first cross-sectional view; the coupling shield electrode comprises a second thickness (height, see Examiner-annotated figure below) in the first cross-sectional view.
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Kondo fails to clearly teach wherein the second thickness is less than the first thickness.
Marchant teaches (e.g. FIG.4J) wherein a second thickness (thickness of 132, see Examiner-annotated figure below) is less than a first thickness (of 130A/130B, see Examiner-annotated figure below).
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It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Kondo with the thicker dielectric within the peripheral region (Marchant’s thick bottom dielectric (TBD) 406, ¶ [0010],[0051]) than in the active region such that the thickness of the shield electrode in the peripheral region is less than a thickness of the shield electrode in the active region as taught by Marchant in order to form the active and peripheral trenches using chemical mechanical polishing (CMP) techniques which has a number of advantages such as improved photo capability by eliminating what is known as "pileup" against topography present in conventional techniques, minimum depth of filed, and improved CD uniformity and/or a highly planar structure with minimal to no structural variations across the array of numerous trenches is thus obtained, and/or the planar surface enables use of lower temperatures in such backend process steps as BPSG reflow and/or the lower backend temperature advantageously enables the use of poly silicide. (Marchant ¶ [0035]).
Regarding claims 2 and 18, Kondo in view of Marchant yields the semiconductor device of claim 1 and the method of claim 17, and Kondo further teaches wherein: the intersecting trench region (154) comprises an intersecting shield electrode (141, ¶ [0018]) in a lower portion of the intersecting trench region and separated from the region of semiconductor material by an intersecting shield electrode dielectric (154, ¶ [0023]); and the intersecting shield electrode comprises a third thickness (as pictured).
Allowable Subject Matter
Claims 10-16 are allowed.
Claims 3-9,19-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior art e.g. Kondo discloses a semiconductor device (FIG. 1-7), comprising:
a region (drift region 113, ¶ [0018]) of semiconductor material comprising a top side and a first conductivity type (“Here, the drift region 113 may be made of first conductivity-type semiconductor” ¶ [0018]);
a first active trench region (one or more of 101, ¶ [0017],[0018]) within the region of semiconductor material and comprising an active shield electrode (135, ¶ [0018]) separated from the region of semiconductor material by an active shield electrode dielectric (133, ¶ [0018]);
an intersecting trench region (154, ¶ [0017]) within the region of semiconductor material and perpendicular to the first active trench region (101) and comprising an intersecting shield electrode (141, ¶ [0018]) separated from the region of semiconductor material by an intersecting shield electrode dielectric (154, ¶ [0023]); and
a first coupling trench region (152, ¶ [0017]) within the region of semiconductor material coupling (in FIG. 1) the first active trench region (101) to the intersecting trench region (154) and comprising a coupling shield electrode (141, ¶ [0018]) separated from the region of semiconductor material by a coupling shield electrode dielectric (133 in 154, “the insulating layer 133 provided in the outer peripheral trench 154, ¶ [0018]);
wherein: the active shield electrode comprises a first thickness (e.g. height, see Examiner-annotated figure below) in a first cross-sectional view;
the coupling shield electrode comprises a second thickness in the first cross-sectional view;
the intersecting shield electrode comprises a third thickness in a second cross-sectional view.
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Marchant teaches (e.g. FIG.4J) wherein a second or third thickness (thickness of 132, see Examiner-annotated figure below) is less than a first thickness (of 130A/130B, see Examiner-annotated figure below), as discussed previously.
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However, prior art fails to reasonably teach or suggest wherein the third thickness if equal to the first thickness together with all of the other limitations of claim 10 as claimed. Claims 11-16 are allowable insofar as they depend upon and include all of the limitations of allowable claim 10.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Eric A. Ward/Primary Examiner, Art Unit 2891
Prosecution Insights