DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-14, in the reply filed on 1/7/26 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (US 2022/0255025).
Regarding claim 1, Yang discloses a display apparatus comprising:
a substrate including (2, fig. 2 and paragraph 0060):
a component area including a transmission area (Abstract, figs. 1-2);
a main area outside the component area (Abstract, figs. 1-2); and
a bending area bent based on a bending axis (Abstract, figs. 1-2);
a buffer layer disposed on the substrate (4, fig. 2 and paragraph 0060);
a first semiconductor layer disposed on the buffer layer (5, fig. 2 and paragraph 0060); and
a first gate insulating layer overlapping the first semiconductor layer (6, fig. 2 and paragraph 0060) and including:
a 1-1st opening corresponding to the bending area (16, fig. 5 and paragraph 0080); and
a 1-1st through-hole exposing a portion of the first semiconductor layer (17’, fig. 5 and paragraph 0079),
wherein a first acute angle formed by an inner surface of the 1-1st opening with respect to an upper surface of the substrate is less than a first contact acute angle formed by an inner surface of the 1-1st through-hole with respect to the upper surface of the substrate (groove 16 vs. via holes 17’, fig. 5 and paragraphs 0079-0080).
Regarding claim 2, Yang further discloses a plurality of auxiliary pixels arranged in the component area (27, 28, fig. 2 and paragraph 0094),
wherein the first gate insulating layer further includes a 2-1st opening corresponding to
the transmission area disposed between the plurality of auxiliary pixels (second 17’, figs. 5, 2).
Regarding claim 3, Yang further discloses wherein a second acute angle formed by an inner surface of the 2-1st opening with respect to the upper surface of the substrate is the same as the first acute angle (figs. 2, 5).
Regarding claim 4, Yang further discloses a second gate insulating layer disposed on the first gate insulating layer (9, fig. 2 and paragraph 0060);
a second semiconductor layer disposed on the second gate insulating layer (10, fig. 2 and paragraph 0060); and
a third gate insulating layer overlapping the second semiconductor layer (15, fig. 2 and paragraph 0060).
Regarding claim 5, Yang further discloses wherein
the second gate insulating layer includes a 1-2nd through-hole corresponding to the 1-
1st through-hole (figs. 2, 5), and
an inner surface of the 1-2ⁿᵈ through-hole and the inner surface of the 1-1st through-
hole form a continuous surface with each other (figs. 2, 5).
Regarding claim 6, Yang further discloses wherein the third gate insulating layer (15, fig. 2) includes a 2-1st through-hole exposing a portion of the second semiconductor layer (10, fig. 2) and includes a second contact acute angle formed by an inner surface of the 2-1st through-hole with respect to the upper surface of the substrate (fig. 2).
Regarding claim 7, Yang further discloses wherein the buffer layer (4, fig. 2) includes a 3-1st opening corresponding to the bending area (right side, fig. 2), and
a third acute angle formed by an inner surface of the 3-1st opening with respect to the
upper surface of the substrate is less than the first acute angle (fig. 2, right side).
Regarding claim 8, Yang further discloses wherein the third acute angle is less than the second contact acute angle (fig. 2).
Regarding claim 9, Yang further discloses wherein, when viewed in a direction
perpendicular to the substrate, an area of the 1-1st opening (groove, right side, fig. 2 above layer 6) is greater than an area of the 3-1st opening (groove, right side, fig. 2 below layer 6).
Regarding claim 10, Yang further disclose wherein, when viewed in a direction
perpendicular to the substrate, the 3-1st opening is disposed in the 1-1st opening (fig. 2 right side).
Regarding claim 11, Yang further discloses wherein the substrate further includes a groove corresponding to the 3-1st opening (fig. 2 right side).
Regarding claim 12, Yang further discloses wherein a fourth acute angle formed by an inner surface of the groove with respect to the upper surface of the substrate is the same as or less than the third acute angle (fig. 2, right side).
Regarding claim 13, Yang further discloses wherein an inner surface of the groove and the inner surface of the 3-1st opening form a continuous surface with each other (fig. 2).
Regarding claim 14, Yang further discloses an organic interlayer insulating layer disposed on the third gate insulating layer (24, fig. 2); and
an organic material layer filling the 1-1st opening and including a same material as the
organic interlayer insulating layer (24, fig. 2).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication 2018/0366586 discloses a display device with a bending area and corresponding groove in conjunction with via holes in the display area.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS M MENZ/Primary Examiner, Art Unit 2897 4/4/26
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