Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-5, 8-14, and 21-28 are pending and rejected. Claims 6, 7, and 15-20 are cancelled. Claims 27 and 28 are newly added. Claims 1, 8, and 21 are amended.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: H2. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 8, 9, 21-24, 26, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang, US 2024/0363407 A1 in view of Hou, US 2022/0081756 A1, as evidenced by Sakuma, US 2009/0087583 A1.
Regarding claims 1 and 3, Zhang teaches a method (abstract), comprising:
positioning a wafer on a wafer support of a physical vapor deposition apparatus, the wafer being separated from a target by a distance exceeding 100 millimeters (where an underlayer is formed on the substrate in a PVD chamber, so as to provide a PVD apparatus, where the substrate is placed on a support and is separated from the target at a distance of about 130 mm to about 160 mm, 0049, 0052, and 0054, such that the distance is within the claimed range), the wafer including an opening that extends through a dielectric layer exposing a conductive feature (where the substrate includes one or more of a dielectric material and includes an opening with a conductive feature disposed at the bottom surface, where the opening is formed in the dielectric layer, 0050 and Fig. 4A);
setting a temperature of the wafer to a room temperature (where the processing temperature is about 15°C to 40°C, such as about 25°C, 0052 and 0054, where the layers are deposited at room temperature, 0047, such that the temperature of the substrate is expected to be room temperature so as to provide deposition at room temperature);
forming a tungsten thin film in the opening by the physical vapor deposition apparatus using a radio frequency power level that exceeds about 5 kilowatts, forming the tungsten thin film including forming a bottom portion that is on and physically abuts an upper surface of the conductive feature exposed by the opening (where a tungsten underlayer, 430, is formed in the opening by PVD and then a second conductive layer, 440, formed of materials such as tungsten is formed by PVD in a PVD chamber, 0052, 0054, and Fig. 4A-C, such that a tungsten thin film is formed in the opening by the PVD apparatus, the tungsten thin film including a bottom portion on the upper surface of the conductive feature exposed by the opening, and where the processing chamber includes an inductive coil configured to form and inductively coupled plasma using an RF power source at powers between about 0 and about 10 kWatts, 0038, such that the power capable of being applied to form the film will overlap the claimed range, where the bottom portion of the conductive film formed by the combination of films 430 and 440 physically abuts the upper surface of the conductive feature, Fig. 4B);
forming a sidewall portion on a sidewall of the dielectric layer that defines the opening that extends into and through the dielectric layer (where the tungsten film includes coating on the sidewalls, Fig. 4B-C, and where a pullback process is provided that removes the first conductive layer and the second conductive layer from the first surface and sidewalls, 0055 and Fig. 4D, indicating that the first and second layers will be formed on the sidewalls),
forming a top portion on an upper surface of the dielectric layer (where the first conductive layer and the second conductive layer are formed on the top surface, Fig. 4B-C, and where during pullback the first conductive layer and the second conductive layer are removed from the first surface 404, 0055 and Fig. 4D, indicating that the first and second conductive layers will be formed on the top surface);
removing the top portion of the tungsten thin film and removing the sidewall portion of the tungsten thin film, and leaving the bottom portion of the tungsten thin film on the conductive feature (where a portion of the first conductive layer and the second conductive layer are removed from the opening to remove at least a portion of the first and second conductive layer from the first surface 404 and sidewalls 410 of the substrate and opening, 0055 and Fig. 4D); and
after removing the top portion and the sidewall portion, forming a tungsten plug in the opening and on and physically abutting the bottom portion by selectively depositing tungsten by a chemical vapor deposition operation (performing selective chemical vapor deposition to deposit a bulk layer 450 of conductive material such as tungsten in the opening, 0057 and Fig. 4E, so as to form a plug such that it will physically abut the conductive layer formed by the first and second conductive layers). It is noted that the claimed conductive film formed by PVD is considered to be the combination of the first and second conductive films of Zhang, where they are both formed by PVD at a distance within the claimed range (0052 and 0054). They teach using the process for electronic devices (0020). They teach that the device maybe a logical device, a gate, a contact pad, a conductive line, via, etc. (0050).
They teach that the conductive layers are formed at or near room temperature (0052 and 0054). From this, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have first set the temperature of the wafer to at or near room temperature before forming the tungsten film because it will provide the desired temperature for the process so that the films are deposited and formed at the desired temperature as opposed to starting the deposition prior to reaching the desired deposition temperature.
They teach that the processing chamber includes an RF bias power source that is coupled between and electrode and RF ground to adjust the bias on the substrate, also referred to as “wafer bias” (0043), suggesting that the substrate is a wafer since the bias is for the wafer or substrate. Therefore, the substrate of Zhang is considered to be a wafer because it is a substrate for electronic devices and because a bias to the substrate is also referred to a wafer bias.
They do not specifically teach the wattage used for depositing the film.
Hou teaches methods that form low resistivity tungsten film on substrates by generating a plasma in a processing volume of a physical vapor deposition chamber with a process gas of krypton and using an RF power with a frequency of about 60 MHz and a magnetron (abstract). They teach that the RF power source operates at a power of greater than zero to approximately 10 kilowatts or more (0020). They teach that the RF power operates at a power of greater than approximately 3 kilowatts to approximately 10 kilowatts or form approximately 6 kilowatts to approximately 10 kilowatts (0020). They teach that the higher the power, the more <110> crystal orientation is generated in the deposited tungsten film (0020). They teach that growth of the <110> crystal orientation leads to a low resistivity tungsten for thin film applications (0017).
From the teachings of Hou, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used an RF power in the range of greater than approximately 3 kilowatts to approximately 10 kilowatts or from approximately 6 kilowatts to approximately 10 kW to form the tungsten layer because Hou teaches such an RF range is desirable for forming low resistivity tungsten by PVD. Therefore, the RF power range will overlap or be within the claimed ranges. According to MPEP 2131.03, “[W]hen, as by a recitation of ranges or otherwise, a claim covers several compositions, the claim is ‘anticipated’ if one of them is in the prior art.” According to MPEP 2144.05, “in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.” Therefore, the first and second tungsten layers will be formed using an RF power level overlapping or within the claimed range such that the combination of the first and second conductive layers are considered to provide the claimed tungsten thin film formed by PVD.
As to the overhang, Zhang teaches that when sputtering in high-aspect ratio features, a disproportionate amount of material accumulates on the edges of the feature where excess material creates overhang (0003 and 0046). They teach reducing overhang to improve bottom coverage (0047). They teach that increasing the spacing reduces overhang that can form at the edges of the opening (0052). They teach that due to the distance from the target and the substrate, overhang at the edges of the opening enable more sputtered material to reach the bottom surface, thereby improving bottom coverage (0060). They teach that the bottom coverage improves from less than 80% to greater than 90% at non-zero substrate biases (0060). They provide a figure indicating that as the bias increases, the bottom coverage goes from greater than 50% to approach 95% as a bias of 250 W (Fig. 6). They teach using a bias of 0 to about 50 W for the first conductive layer and from about 0 to about 350 W, about 125 to 175 W, or about 150 W for the second conductive layer (0052 and 0054). As evidenced by Sakuma, bottom coverage is defined as a film thickness b of the film on the bottom of the recess/a film thickness a of the film on the wafer upper surface, i.e., b/a (0057). Therefore, since Zhang indicates that the bottom coverage is in the range of greater than 50% or greater than 90%, depending on the bias, where the bias includes ranges of 0 to 175 W (which is indicated as having a bias of less than 100%), the resulting film are also expected to include a range in which the second thickness on the upper surface is greater than the first thickness on the bottom surface. Further, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention that the films will also include a top portion partially overlapping the opening because Zhang teaches that overhang is reduced but not eliminated and that it is a common feature with PVD such that there is expected to be at least some overhang in the films.
Further, since Zhang in view of Hou as evidenced by Sakuma suggest the process of claim 1, where the film is deposited using distances, powers, and temperature overlapping the claimed ranges (as discussed further below for claims 2, 4, and 5), the resulting films are also expected to have thicknesses and overlap meeting the claimed ranges. According to MPEP 2112.01 I, “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977)”.
Regarding claim 2, Zhang in view of Hou and as evidenced by Sakuma suggest the process of claim 1. As discussed above, Zhang teaches that the distance between the target and the substrate is in the range of about 130 mm to about 160 mm (0052 and 0054), so as to overlap the claimed range.
Regarding claim 4, Zhang in view of Hou and as evidenced by Sakuma suggest the process of claim 1. As discussed above, Zhang teaches that the processing temperature is about 15°C to 40°C, such as about 25°C (0052 and 0054), where the layers are deposited at room temperature (0047), such that the temperature of the substrate is expected to be about 15°C to 40°C, such as about 25°C since that is the processing temperature for deposition, where if the substrate temperature were higher, then the deposition temperature of the film would be higher. Therefore, the temperature of the substrate or wafer will be set to be within or overlapping the claimed range. According to MPEP 2131.03, “[W]hen, as by a recitation of ranges or otherwise, a claim covers several compositions, the claim is ‘anticipated’ if one of them is in the prior art.” According to MPEP 2144.05, “in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.”
Regarding claim 5, Zhang in view of Hou and as evidenced by Sakuma suggest the process of claim 4. Zhang teaches that the first conductive layer and the second conductive layer are formed at the temperature of about 15°C to 40°C or about 25°C (0052 and 0054). They teach that depositing the layer by PVD at a low temperature, it prevents intermixing between the conductive layer and the substrate, resulting in a smoother boundary that reduces interface scattering and resistivity of the associated conductive features (0047). They teach annealing after deposition (0056 and 0057). From this, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have maintained the substrate at a temperature of about 15°C to 40°C or about 25°C because Zhang teaches that such a process temperature is desirable for depositing the first and second tungsten film by PVD, where the temperature reduced intermixing such that it will be expected to provide the desired temperature throughout the process and prevent intermixing as desired.
Regarding claim 8, as discussed above for claim 1, Zhang in view of Hou and as evidenced by Sakuma suggest positioning a wafer on a substrate support of a PVD apparatus, the substrate or wafer including an opening that extends through a dielectric layer exposing a conductive feature; setting a temperature of the wafer to room temperature; after setting the temperature of the wafer to the room temperature, forming a tungsten thin film in the opening by the PVD apparatus, forming the tungsten thin film including forming a bottom portion that is on and physically abutting an upper surface of the conductive feature exposed by the opening, and the bottom portion having a first thickness; forming a top portion that is on an upper surface of the dielectric layer through which the opening extends, and the top portion has a second thickness that is greater than the first thickness of the bottom portion; and forming a sidewall portion that is on a sidewall of the dielectric layer exposed by the opening and the sidewall portion extends from the top portion to the bottom portion; after forming the tungsten thin film, removing the top portion and the sidewall portion of the tungsten thin film from over the opening; and forming a tungsten plug in the opening on, and physically abutting the bottom portion by selectively depositing tungsten by a CVD operation.
Zhang further teaches that the substrate support may be an electrostatic chuck (0032).
Regarding claim 9, Zhang in view of Hou and as evidenced by Sakuma suggest the process of claim 8. As discussed above for claim 4, they further suggest using a temperature within or overlapping the range of claim 9. According to MPEP 2131.03, “[W]hen, as by a recitation of ranges or otherwise, a claim covers several compositions, the claim is ‘anticipated’ if one of them is in the prior art.” According to MPEP 2144.05, “in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.”
Regarding claims 21 and 23, as discussed above for claims 1 and 3-8, Zhang in view of Hou and as evidenced by Sakuma suggest positioning a wafer on a wafer support inside a physical-vapor-deposition apparatus, the wafer including an opening that exposes a conductive feature; separating the wafer from a tungsten target (since tungsten is formed from the process) by a wafer-to-target separation distance that is within the claimed range; maintaining the wafer at a temperature within or overlapping the claimed range while operating a first power generator at a radio-frequency power level overlapping or within the claimed ranges to sputter tungsten and thereby form a tungsten thin film on the wafer and in an opening of the wafer defined by one or more dielectric layers of the wafer, forming the tungsten thin film including: forming a bottom portion on an upper surface of the conductive feature exposed by the opening, and the bottom portion having a first thickness; forming a sidewall portion on a sidewall defined by one or more dielectric layers, and the sidewall defines the opening; and forming a top portion on a field surface of an uppermost dielectric layer of the one or more dielectric layers, the top portion partially overlaps the opening, and the top portion has a second thickness greater than the first thickness; removing the sidewall portion and the top portion of the tungsten thin film from over the opening; and selectively depositing tungsten by chemical vapor deposition to fill the opening with a tungsten plug on and physically abutting the bottom portion.
Regarding claim 22, Zhang in view of Hou and as evidenced by Sakuma suggest the process of claim 21. As discussed above for claim 2, they further suggest using a spacing range overlapping the claimed range.
Regarding claim 24, Zhang in view of Hou and as evidenced by Sakuma suggest the process of claim 21. Zhang further teaches that the first conductive layer has a thickness of less than 20 angstroms and the second conductive layer has a thickness of greater than 20 angstroms (0006). They teach that the thickness of underlayer 430, i.e., the first conductive layer is in the range of about 4 angstroms to about 50 angstroms, such as about 4 angstroms to about 20 angstroms (0052). They teach that the second conductive layer 440 is deposited with a thickness of about 40 angstroms, or of about 20 angstroms to about 100 angstroms, such as about 30 angstroms to about 60 angstroms, etc. (0054). It is noted that the first and second conductive layers are deposited with the same temperature and spacing conditions by PVD (0052 and 0054). Therefore, the claimed tungsten thin film can be considered the combination of the first and second tungsten layer of Zhang so as to provide physically abutting the conductive feature and the CVD plug, such that the thickness of the tungsten thin film will overlap of be within the claimed range. According to MPEP 2131.03, “[W]hen, as by a recitation of ranges or otherwise, a claim covers several compositions, the claim is ‘anticipated’ if one of them is in the prior art.” According to MPEP 2144.05, “in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.”
Regarding claim 26, Zhang in view of Hou and as evidenced by Sakuma suggest the process of claim 21. Zhang further teaches that the selectively depositing tungsten is performed at a temperature higher than the temperature used during PVD (0052, 0054, and 0057).
Regarding claim 27, Zhang in view of Hou and as evidenced by Sakuma suggest the process of claim 1. As discussed above for claim 1, Zhang teaches that the bottom coverage ranges from greater than 50% to about 95% depending on the wafer bias (Fig. 6). They teach forming the first conductive layer with low or no bias to minimize intermixing and provide a low-resistivity alpha tungsten film (0052-0053). They teach that the second film is deposited as higher resistivity beta phase tungsten and then annealed to provide alpha phase (0053-0054 and 0056). They teach that the first film has a thickness in the range of 4-50 angstroms, 4 to 20 angstroms, or 4 to 12 angstroms (0052). They teach that the second layer has a thickness of 20 to 100 angstroms (0054). Therefore, when the thickness of the bottom layer (combination of the first and second conductive layers) is in the range of 4 to 150 Angstroms, the thickness of the top portion is also expected to include a range overlapping the claimed range based on the bottom coverage ranging from greater than 50% to 95%. For example, if the total bottom coverage is 65%, the resulting film thickness would range from about 6 to 154 angstroms and if the total bottom coverage is 95%, the resulting film thickness would range from about 4 to 105 angstroms. According to MPEP 2144.05, “in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.”
Claims 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Hou and as evidenced by Sakuma as applied to claim 8 above, and further in view of Takehara, US 2007/0020903 A1.
Regarding claims 10 and 11, Zhang in view of Hou and as evidenced by Sakuma suggest the process of claim 8. Zhang further teaches that the support 226 may be an electrostatic chuck, a heater, or a combination thereof (0032).
They do not teach disabling the heater of the chuck.
Takehara teaches a method for making a film stack containing one or more silicon-containing layers and one or more metal-containing layers (abstract). They teach that a substrate support includes at least one heater connected to a power source that controllably heats the support assembly and the substrate (0146). They teach that the temperature of the heater can be set at about 100°C or lower, such as between about 20°C to about 80°C, depending on the deposition processing parameters for the material layer being deposited (0147). They teach that the heater can be turned off with only hot water flowing inside the substrate support assembly to control the temperature of the substrate during deposition, resulting in a substrate temperature of about 80°C or lower for a low temperature deposition process (0147).
From the teachings of Takehara, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have turned off the heat to the electric chuck during the process such that it will be off throughout the process of forming the tungsten thin film because Zhang teaches performing deposition at room temperature where the ESC can include a heater and Takehara teaches that a heater in a support can be turned off when using low temperature deposition processes such that it will be expected to provide the substrate at room temperature as desired without heating the substrate. Further, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have disabled or turned off the heater for the duration of the deposition of the tungsten thin film because Zhang teaches using room temperature for the deposition process such that the entirety of the process will be done at room temperature and not require heating.
Regarding claims 12-14, Zhang in view of Hou and Takehara and as evidenced by Sakuma suggest the process of claim 10. They do not specifically teach that the tungsten plug includes smaller grain sizes than that of the bottom portion or that there is a discernable interface between the plug and the bottom portion, however, since they provide the claimed process, including using temperatures within or overlapping the claimed ranges, where the CVD process has a higher temperature than the PVD process (as discussed above), the resulting thin film and plug are expected to have the claimed features. According to MPEP 2112.01 I, “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977)”.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Hou and as evidenced by Sakuma as applied to claim 21 above, and further in view of Romero, US 2015/0170961 A1 and Wang, US 2023/0107536 A1.
Regarding claim 25, Zhang in view of Hou and as evidenced by Sakuma suggest the process of claim 21. Zhang teaches performing selective CVD to deposit the bulk layer of tungsten (0057).
They do not teach using ALD.
Romero teaches selective area deposition of metal films by ALD and CVD where the metal is selectively deposited on a metal surface instead of a dielectric surface (abstract). They teach that the precursor used in the process can include tungsten as a metal center for N,N’-dialkyl-diazabutadiene ligands (0034). They teach using ALD or CVD to deposit the metal film with the N,N’-dialkyl-diazabutadiene metal precursor and a co-reactant such as hydrogen or ammonia, i.e., reducing agents (0032). They teach fabricating a metallization structure by forming a plurality of tungsten contacts in a dielectric layer to provide exposed regions of the dielectric layer and exposed regions of the tungsten contacts and then selectively depositing a metal such as tungsten on the contacts using the ALD or CVD process (0097).
Wang teaches a structure of a substrate including a tungsten-containing layer including a nucleation layer and a fill layer (abstract). They teach forming a nucleation layer by ALD, where the ALD process includes repeating cycles of alternately exposing the substrate to a tungsten-containing precursor and exposing the substrate to a reducing agent (0069). They teach that the processing region is purged between the alternating exposures (0069).
From the teachings of Romero and Wang, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have deposited the bulk tungsten layer using a selective ALD process as a simple substitution for the selective CVD process by alternating a tungsten precursor and a reducing agent (hydrogen or ammonia) separated by purge steps because Romero teaches that ALD can be used to selectively deposit metal on a tungsten contact as an alternative to selective CVD and Wang teaches that such a sequence is used for ALD such that it will be expected to provide the desired and predictable result of selectively forming the bulk tungsten layer selectively by ALD.
Claims 27 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Hou and as evidenced by Sakuma as applied to claim 21 above, and further in view of Lee, US 2022/0068709 A1 (note the second inventor is used to differentiate between Wang references).
Regarding claims 27 and 28, Zhang in view of Hou and as evidenced by Sakuma suggest the process of claim 1. As discussed above for claim 1, Zhang teaches that the bottom coverage ranges from greater than 50% to about 95% depending on the wafer bias (Fig. 6). They teach forming the first conductive layer with low or no bias to minimize intermixing and provide a low-resistivity alpha tungsten film (0052-0053). They teach that the second film is deposited as higher resistivity beta phase tungsten and then annealed to provide alpha phase (0053-0054 and 0056). They teach that the first film has a thickness in the range of 4-50 angstroms, 4 to 20 angstroms, or 4 to 12 angstroms (0052). They teach that the second layer has a thickness of 20 to 100 angstroms (0054). Zhang teaches that increasing the spacing between the target and the substrate improves the bottom coverage (0052). They teach that the spacing ranges from about 80 mm to 200 mm, such as about 130 mm to about 160 mm (0052). They teach that Fig. 6 shows that increasing the target to substrate distance from 95 mm to 145 mm improves the bottom coverage, from less than 80% to greater than 90% (0060 and Fig. 6).
They do not teach that the thickness of the top portion and bottom portion meet the requirements of claims 27 and 28.
Lee teaches method to provide electronic devices comprising tungsten film stacks (abstract). They teach forming a tungsten liner by PVD and then filling with a tungsten film formed by CVD over the tungsten liner (abstract). They teach depositing the tungsten liner using PVD with no bias power to provide alpha-W (0017). They teach that using no bias results in improved properties in terms of grains size and orientation to improve the stack resistivity of the tungsten stack comprising the liner and tungsten film (0017). They teach forming the tungsten liner layer with a thickness in the range of from about 5 to 35 angstroms (0038).
From the teachings of Lee, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the process of Zhang in view of Hou and as evidenced by Sakuma to have deposited a single tungsten liner layer having a thickness of about 5 to 35 A using no bias in the PVD process because Lee teaches that a single layer deposited using no bias provides alpha tungsten on which a CVD tungsten gapfill layer can be deposited, where the alpha tungsten liner improves the resistivity of the stack such that it will be expected to provide a desirable stack to prevent intermixing as desired by Zhang while also providing desirable resistivity. Therefore, the tungsten thin film will be deposited to a thickness of about 5 to 35 A using no bias while abutting the conductive feature and the CVD plug so as to provide a thickness overlapping the range of claim 28. Since Zhang indicates that the spacing changes the bottom coverage and the spacing taught by Zhang in view of Hou and Lee and as evidenced by Sakuma overlaps the claimed range, where the films are deposited at temperatures and powers overlapping the claimed ranges (as discussed above for claims 1-5, the resulting coverage is also expected to result in a top portion having a thickness overlapping the claimed range. According to MPEP 2144.05, “in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.” According to MPEP 2112.01 I, “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977)”.
Response to Arguments
Applicant's arguments filed 1/12/2026 have been fully considered.
In light of the amendment to the specification, the previous drawing objection over numerals 200 and 202 has been withdrawn. However, the objection over H2 remains.
Regarding Applicant’s arguments over Zhang, as discussed above, the reference is considered to suggest the claimed features, other than the RF power, where the combination of the first and second conductive films provide the claimed conductive film because they are formed at the required temperature and spacing. The evidentiary reference of Sakuma was provided to indicate the definition of bottom coverage as described by Zhang.
In light of the addition of claims 27 and 28, a new reference of Lee was included to suggest the thickness of the layers.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTINA D MCCLURE/Examiner, Art Unit 1718 /GORDON BALDWIN/Supervisory Patent Examiner, Art Unit 1718
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