DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election without traverse of Group I (claims 1-20) in the reply filed on February 13rd, 2026 is acknowledged.
Claim 21 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5, 7-10 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Usenko (Pub. No.: US 2019/008466 A1).
Regarding claim 1, Usenko discloses a method of preparing a silicon-on- insulator structure in Figs. 2A-2K, the method comprising: forming an epitaxial silicon layer (epi layer 102) on a front surface of a single crystal silicon donor substrate (front surface of substrate 100 being single-crystalline silicon) (see Fig. 2A and [0011-0012]); forming a dielectric layer (oxide layer 104) on the epitaxial silicon layer to thereby form an epitaxial donor structure comprising the single crystal silicon donor substrate, the epitaxial silicon layer, and the dielectric layer (see Fig. 2B and [0016]); bonding the dielectric layer of the epitaxial donor structure to a front surface of a handle structure (front surface of handle wafer 110), the handle structure comprising a single crystal semiconductor handle substrate, to thereby form a bonded structure comprising the handle structure, the dielectric layer, the epitaxial silicon layer, and the single crystal silicon donor substrate (see Fig. 2D and [0029-0031]); and removing the single crystal silicon donor substrate (removing substrate 100) and a portion of the epitaxial silicon layer from the bonded structure to thereby form the silicon-on-insulator structure comprising the handle structure (portion of epi layer 102 above etch stop layer 106 being removed), the dielectric layer, and a silicon device layer (the remaining epi layer 102) (see Figs. 2F-2K and [0035-0040]).
Regarding claim 2, Usenko discloses method of claim 1, further comprising annealing the silicon-on-insulator structure at a temperature and for a duration sufficient to smooth a surface of the silicon device layer (annealing is performed at temperature 1000-1200oC) (see Fig. 2J and [0041-0042], [0044]).
Regarding claim 3, Usenko discloses method of claim 2, further comprising wherein the annealing is performed at the temperature of between 1000-1200oC (annealing is performed at temperature 1000-1200oC) (see Fig. 2J and [0041-0042], [0044]).
Regarding claim 5, Usenko discloses method of claim 2, wherein the annealing is performed in the presence of an inert gas, hydrogen (H-2), or a combination thereof (argon or Hydrogen being used) (see [0042]).
Regarding claim 7, Usenko discloses method of claim 1, wherein the epitaxial silicon layer is substantially free of nitrogen (never mention of presence of nitrogen and free of defect) (see [0015-0016]).
Regarding claim 8, Usenko discloses method of claim 1, wherein the epitaxial silicon layer is substantially free of oxygen (never mention of presence of oxygen and free of defect) (see [0015-0016]).
Regarding claim 9, Usenko discloses method of claim 1, wherein a thickness of the epitaxial silicon layer is between 0.5 µm to 5 µm (see [0015]).
Regarding claim 10, Usenko discloses method of claim 1, wherein a thickness of the epitaxial silicon layer is between 1 µm to 3 µm (see [0015]).
Regarding claim 18, Usenko discloses method of claim 1, wherein the single crystal silicon donor substrate is substantially free of nitrogen as dopant (no mentioning that substate 100 is not being doped with nitrogen as dopant) (see [0011-0013]).
Regarding claim 19, Usenko discloses method of claim 1, wherein the method does not include chemical mechanical polishing of the silicon device layer (see Fig. 2K and [0043-0046]).
Regarding claim 20, Usenko discloses method of claim 1, further comprising implanting ions through a surface of the epitaxial donor structure to thereby form a cleave plane (implantation of ion in process 105 to form etch stop layer 106) in the epitaxial silicon layer, wherein removing the single crystal silicon donor substrate and the portion of the epitaxial silicon layer from the bonded structure comprises cleaving the bonded structure at the cleave plane to thereby form the silicon-on-insulator structure (removing upper portion of epi layer 102) (see Figs. 2F-2H and [0023-0026], [0035-0037]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Usenko (Pub. No.: US 2019/008466 A1). as applied to claims 2 and 1 above.
Regarding claim 4, Usenko discloses method of claim 2, but fails to disclose wherein the annealing is performed at the duration of between 15 minutes to 10hrs.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have the method comprising wherein the annealing is performed at the duration of between 15 minutes to 10hrs because Usenko discloses the method of recrystallization and the method of ramping up temperature and therefore would be conventional to have between 15minutes- to 10hrs to get up to the annealing temperature and target to smooth the surfaces. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Regarding claim 11, Usenko discloses method of claim 1, wherein a thickness of the silicon device layer is less than 100 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have the method comprising wherein a thickness of the silicon device layer is less than 100 nm because the claimed thickness is standard thickness for forming semiconductor devices. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Regarding claim 12, Usenko discloses method of claim 1, wherein a thickness of the silicon device layer is less than 25 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have the method comprising wherein a thickness of the silicon device layer is less than 25 nm because the claimed thickness is standard thickness for forming semiconductor devices. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Usenko (Pub. No.: US 2019/008466 A1) as applied to claim 2 above, and further in view of Usenko (Pub. No.: 2013/0089968 A1), hereinafter as Usenko968.
Regarding claim 6, Usenko discloses method of claim 2, but fails to disclose wherein a surface of the silicon device layer is characterized by a lack of nanometer-sized recesses that affect a roughness of the surface of the silicon device layer as measured by atomic force microscopy.
Usenko968 discloses a method of comprising wherein a surface of a silicon device layer (surface of layer 122) is characterized by a lack of nanometer-sized recesses that affect a roughness of the surface of the silicon device layer as measured by atomic force microscopy (roughness of layer 122 is determined or affected by any nanometer-sized recesses) (see Fig. 5-7 and [0070-0072).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the method of using AFM to characterize the silicon device layer of Usenko968 into the method of Usenko for verifying the roughness of the silicon device layer is determined by the presence of the nanometer-sized recessed because it is conventional that the roughness of any device surfaces can be increased by the presence of concave-convex surfaces of the deice layer and this can be determined by method of using AFM with lower manufacturing cost.
Claims 13-15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Usenko (Pub. No.: US 2019/008466 A1) as applied to claim 1 above, and further in view of Falster et al. (Pub. No.: 2007/0105279 A1), hereinafter as Falster.
Regarding claim 13, Usenko discloses method of claim 1, but fails to disclose, wherein the single crystal silicon donor substrate is sliced substantially on-axis from a single crystal silicon ingot, and wherein the single crystal silicon donor substrate has an interstitial oxygen concentration of less than 2.5x1017 atoms/cm3 and is substantially free from nitrogen as dopant.
Falster discloses a method comprising a single crystal silicon donor substrate (substrate 1) is sliced substantially on-axis from a single crystal silicon ingot, wherein the single crystal silicon donor substrate is sliced substantially on-axis from a single crystal silicon ingot (see Fig. 1 and [0012-0013]), and wherein the single crystal silicon donor substrate has an interstitial oxygen concentration of less than 2.5x1017 atoms/cm3 (see [0007]) and is substantially free from nitrogen as dopant (no mentioning about doping nitrogen).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the method of silicon ingot for forming single crystal silicon donor substrate with the claimed oxygen concentration of Falster into the method of Usenko because the modified method would provide the lowest cost and most reliable donor substrate for forming semiconductor device.
Regarding claim 14, the combination of Usenko and Falster discloses method of claim 13, but fails to disclose wherein on-axis deviation of an angle at which the single crystal silicon donor substrate is sliced from the single crystal silicon ingot is less than +/- 0.10.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have the method comprising wherein on-axis deviation of an angle at which the single crystal silicon donor substrate is sliced from the single crystal silicon ingot is less than +/- 0.10 because controlling the deviation of the angle would improve the defects on the surface of the epitaxial layer. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Regarding claim 15, the combination of Usenko and Falster discloses method of claim 13, but fails to disclose wherein on-axis deviation of an angle at which the single crystal silicon donor substrate is sliced from the single crystal silicon ingot is less than +/- 0.070.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have the method comprising wherein on-axis deviation of an angle at which the single crystal silicon donor substrate is sliced from the single crystal silicon ingot is less than +/- 0.070 because controlling the deviation of the angle would improve the defects on the surface of the epitaxial layer. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Regarding claim 17, Usenko discloses method of claim 1, but fails to disclose, wherein the single crystal silicon donor substrate has an interstitial oxygen concentration of less than 2.5x1017 atoms/cm3.
Falster discloses a method comprising a single crystal silicon donor substrate (substrate 1) is sliced substantially on-axis from a single crystal silicon ingot, wherein the single crystal silicon donor substrate is sliced substantially on-axis from a single crystal silicon ingot (see Fig. 1 and [0012-0013]), and wherein the single crystal silicon donor substrate has an interstitial oxygen concentration of less than 2.5x1017 atoms/cm3 (see [0007]) and is substantially free from nitrogen as dopant (no mentioning about doping nitrogen).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the method of silicon ingot for forming single crystal silicon donor substrate with the claimed oxygen concentration of Falster into the method of Usenko because the modified method would provide the lowest cost and most reliable donor substrate for forming semiconductor device.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Usenko (Pub. No.: US 2019/008466 A1) as applied to claim 1 above, and further in view of Kitada (Pub. No.: 2015/0155299 A1).
Regarding claim 13, Usenko discloses method of claim 1, but fails to disclose wherein the epitaxial silicon layer is formed by chemical vapor deposition.
Kitada discloses a method comprising forming an epitaxial silicon layer (layer 20Xb) on a silicon substrate (substrate 20Xa) by chemical vapor deposition (see Fig. 2 and [0049]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the method of using chemical vapor deposition of Kitada to form the epitaxial silicon layer of Usenko because it is conventional to use the method of chemical vapor deposition to form epitaxial silicon layer substrate for low manufacturing cost and providing reliable silicon material.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818