DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 10-16 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/14/2026.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Circuit Board”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Zheng Xin, CN-115113463, in view of Zhang Yu-xin, CN 211905186.
Regarding Claim 1, Zheng Xin discloses; A circuit board, comprising: a main board, comprising: a first external structure (Fig. 1 and Page 4; ¶ 2; circuit control system 70); a second external structure (Fig. 1 and Page 4; ¶ 2; bottom metal conductor 13); and an internal structure (Fig. 1 and Page 4; ¶ 2; top metal conductor 13, heat source module 20) disposed between the first external structure and the second external structure, wherein the internal structure, the first external structure, and the second external structure are stacked along a first direction (Fig. 1 and Page 4; ¶ 2; top metal conductor 13, heat source module 20, circuit control system 70 and bottom metal conductor 13 are stacked vertically), wherein the internal structure includes: a first internal circuit layer (Fig. 1 and Page 4; ¶ 2; circuit layer on substrate 21); a second internal circuit layer (Fig. 1 and Page 4; ¶ 2; top metal conductor 13); and an insulating layer (Fig. 1 and Page 4; ¶ 2; insulating ceramic cold end 14a) disposed between the first internal circuit layer and the second internal circuit layer, wherein the insulating layer, the first internal circuit layer, and the second internal circuit layer are stacked along the first direction (Fig. 1; circuit layer on substrate 21, insulating ceramic cold end 14a and top metal conductor 13 stacked vertically); a second bonding layer (Fig. 1 and Page 7; ¶ 2; insulating aerogel felt 16) disposed between the internal structure and the second external structure, wherein the second bonding layer connects (Fig. 1 and Page 7; ¶ 2; insulating aerogel felt 16 connects top metal conductor 13, heat source module 20 and bottom metal conductor 13) to the internal structure and the second external structure; a thermistor layer (Fig. 1 and Page 5; ¶ 6; thermistor 60) disposed (Fig. 1 and Page 4; ¶ 2; thermistor 60 disposed on insulating ceramic cold end 14a and circuit layer on substrate 21) on the insulating layer and the first internal circuit layer; and a plurality of N-type semiconductor units (Fig. 1 and Page 6; ¶ 1; N-type semiconductor 11) and a plurality of P-type semiconductor units (Fig. 1 and Page 6; ¶ 1; P-type semiconductor 12), wherein the N-type semiconductor units and the P-type semiconductor units are embedded in the second bonding layer (Fig. 1 and Page 7; ¶ 2; insulating aerogel felt 16) and electrically connect (Fig. 1 and Page 6; ¶ 1; metal conductor 13 is respectively connected with the two ends of the P-type semiconductor 12 and the N-type semiconductor 11) to the second internal circuit layer and the second external structure, wherein the N-type semiconductor units and the P-type semiconductor units alternately arrange (Fig. 1 and Page 6; ¶ 1; P-type semiconductor 12 and N-type semiconductor 11 are alternately arranged in parallel and stacked horizontally) along a second direction perpendicular to the first direction, and an orthogonal projection of the N-type semiconductor units and the P-type semiconductor units on the insulating layer overlaps (Fig. 1; P-type semiconductor 12 and N-type semiconductor 11 are located under thermistor 60) an orthogonal projection of the thermistor layer on the insulating layer. Zheng Xin substantially discloses the invention including the internal structure, the first external structure and the thermistor layer but is silent about a first bonding layer disposed between the internal structure and the first external structure, wherein the first bonding layer connects to the internal structure and the first external structure and the thermistor layer embedded in the first bonding layer. However, Zhang Yu-xin shows that a first bonding layer (Fig. 2 and Page 3; ¶ 5, Page 4; ¶ 1; substrate 101 is filled with filler 103 disposed between N, P type semiconductors unit TEC 3 and sensing signal processing chip 2) disposed between the internal structure and the first external structure, wherein the first bonding layer connects (Fig. 2 and Page 4; ¶ 1; substrate 101 is filled with filler 103 connects N, P type semiconductors unit TEC 3 and sensing signal processing chip 2) to the internal structure and the first external structure and the thermistor layer embedded in the first bonding layer (Fig. 2 and Page 4; ¶ 1; embedded with a thick film thermistor 5). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Zheng Xin by providing a first bonding layer disposed between the internal structure and the first external structure, wherein the first bonding layer connects to the internal structure and the first external structure and the thermistor layer embedded in the first bonding layer so that the embedded position of the thick film thermistor is aligned with the integrated circuit chip area which is more sensitive to the temperature in the vertical direction (Page 4; ¶ 2).
Regarding Claim 2, Zheng Xin discloses; the second internal circuit layer comprises a plurality of cold ends (Fig. 1 and Page 6; ¶ 3; insulating ceramic cold end 14a connected with a plurality of top metal conductor 13), and the second external structure comprises a plurality of hot ends (Fig. 1 and Page 6; ¶ 3; insulating ceramic hot end 14b connected with a plurality of bottom metal conductor 13), wherein an ith N-type semiconductor unit is adjacent to an ith P-type semiconductor unit (Fig. 1 and Page 6; ¶ 1; P-type semiconductor 12 and N-type semiconductor 11 are alternately arranged in parallel), the ith N-type semiconductor unit and the ith P-type semiconductor unit connect to a same cold end (Fig. 1 and Page 6; ¶ 2; 1 #, 3 #, 5 # is N-type semiconductor 11, 2 #, 4 #, 6 # is P-type semiconductor 12. 1 #, 2 # upper end is connected with the same metal conductor 13), and the ith P-type semiconductor unit and a (i+1)th N-type semiconductor unit connect to a same hot end, where i is a positive integer (Fig. 1 and Page 6; ¶ 2; 2 #, 3 # lower end connected with the same metal conductor 13 and the S-like structure extends in the left and right directions, the metal conductor 13 is located above the upper and lower parts of the S-like structure).
Regarding Claim 3, Zheng Xin discloses; the N-type semiconductor units and the P-type semiconductor units electrically connect to the second external structure (Fig. 1 and Page 6; ¶ 1; bottom metal conductor 13 is respectively connected with the two ends of the P-type semiconductor 12 and the N-type semiconductor 11).
Regarding Claim 4, Zheng Xin discloses; a thermal conductive layer (Fig. 1 and Page 4; ¶ 2; bottom heat-conducting silicone grease 50) disposed on the second external structure, wherein the thermal conductive layer connects (Fig. 1 and Page 4; ¶ 2; bottom heat-conducting silicone grease 50 connects bottom metal conductor 13, insulating aerogel felt 16) to the second external structure and the second bonding layer; and a dissipation reinforcing layer (Fig. 1 and Page 4; ¶ 2; fin radiator 40) disposed on the thermal conductive layer.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Zheng Xin, CN-115113463, in view of Zhang Yu-xin, CN 211905186 as applied to claims 1-4 above, and further in view of Muramatsu - JP-H05243621
Regarding claim 5, Zheng Xin discloses; a thermal conductive layer (Fig. 1 and Page 4; ¶ 2; top heat-conducting silicone grease 50) disposed on the thermistor layer (Fig. 1 and Page 5; ¶ 6; thermistor 60). Zheng Xin substantially discloses the invention including thermistor and thermal conductive layer but is silent about an image sensor disposed on the thermal conductive layer. However, Muramatsu shows that an electronic cooler 50 comprising an image sensor chip 18 and a plurality of Peltier elements 26 in contact with the back surface of the chip 18 (Fig. 7-8 and Page 2; ¶ 7). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Zheng Xin in view of Zhang Yu-xin by providing an image sensor disposed on the thermal conductive layer so that an image sensor for converting a light input position into time-series information is one in which photodiodes are arranged one-dimensionally or two-dimensionally (Page 1; ¶ 3).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Zheng Xin, CN-115113463, in view of Zhang Yu-xin, CN 211905186 as applied to claims 1-4 above, and further in view of Ahn - US 6288343.
Regarding claims 6-7, Zheng Xin substantially discloses the invention including the first external structure and the second external structure but is silent about a protruding portion of the internal structure protrudes from a sidewall of the first external structure and a sidewall of the second external structure, wherein the main board further comprising: a first cover layer covering the protruding portion of the internal structure; and a second cover layer covering the protruding portion of the internal structure; wherein the circuit board further comprising: an extending board, wherein the extending board electrically connects to the protruding portion of the internal structure in claim 6 and the extending board comprises a data processor and a driving circuit in claim 7. However, Ahn shows that source PCB 200 is integrated with connector PCB 200a through a connection member 228. The connection member 228 includes the first layer 210 of FR4, a pair of conductive pattern layers 218 disposed respectively on both surfaces of the first layer 210, and protective layers 220 and 225 made of polyimide disposed on both surfaces of the conductive pattern layers 218 (Fig. 2-3 and Col.3; Ln.20-23, 29-33) and also the gate lines 20 and data lines 30 extend to the both side edges of the TFT substrate 10 and are exposed to the outside for the connection with the drive PCBs 100, 200 (Fig. 1-3 and Col.3; Ln.5-8). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Zheng Xin in view of Zhang Yu-xin by providing a protruding portion of the internal structure protrudes from a sidewall of the first external structure and a sidewall of the second external structure, wherein the main board further comprising: a first cover layer covering the protruding portion of the internal structure; and a second cover layer covering the protruding portion of the internal structure; wherein the circuit board further comprising: an extending board, wherein the extending board electrically connects to the protruding portion of the internal structure in claim 6 and the extending board comprises a data processor and a driving circuit in claim 7, so that a printed circuit board in which a source PCB and a connector PCB have a multi-layered structure and the connector PCB that connects the source PCB with the control PCB is integrated with the source PCB (Col.1; Ln.11-14).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Zheng Xin, CN-115113463, in view of Zhang Yu-xin, CN 211905186 as applied to claims 1-4 above, and further in view of Matsunami - WO-2015005362
Regarding claims 8-9, Zheng Xin substantially discloses the invention including the first external structure and the second external structure but is silent about a solder mask layer disposed on the first external structure and on the second external structure in claim 8 and a protecting layer on the first external structure, wherein the protecting layer includes a nickel-gold layer in claim 9. However, Matsunami shows that the electrode protective layer 80 includes at least one metal layer, for example, nickel (Ni), gold (Au) / nickel (Ni) laminated structure, tin (Sn), nickel (Ni) -containing alloy or metal (Fig. 2a and Page 4; ¶ 3) and a solder layer 90 containing 85% or more of lead (Pb) (Fig. 2a and Page 4; ¶ 3). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Zheng Xin in view of Zhang Yu-xin by providing a solder mask layer disposed on the first external structure and on the second external structure in claim 8 and a protecting layer on the first external structure, wherein the protecting layer includes a nickel-gold layer in claim 9, so that an electrode protective layer mainly for the purpose of preventing the oxidation of the electrode and improving the reactivity with the solder (Page 4; ¶ 3).
Conclusion
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/AZM PARVEZ/
Examiner
Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892