Prosecution Insights
Last updated: April 19, 2026
Application No. 18/455,156

PACKAGE WITH EMBEDDED TRACES

Final Rejection §103
Filed
Aug 24, 2023
Examiner
TRAN, TAN N
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Panjit International Inc.
OA Round
2 (Final)
86%
Grant Probability
Favorable
3-4
OA Rounds
2y 3m
To Grant
97%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
941 granted / 1088 resolved
+18.5% vs TC avg
Moderate +10% lift
Without
With
+10.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
45 currently pending
Career history
1133
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
49.9%
+9.9% vs TC avg
§102
34.9%
-5.1% vs TC avg
§112
7.2%
-32.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1088 resolved cases

Office Action

§103
DETAILED ACTION Claim Objections 1. Claim 4 is objected to because of the following informalities: In claim 4, line 3, “the first conducting layers has” should be changed to “the first conducting layer has” Appropriate correction is required. Claim Rejections - 35 USC § 103 2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 3. Claims 1 - 10 are rejected under 35 U.S.C. 103 as being unpatentable over Pagaila (9142431) in view of Hsu (6882057). With regard to claim 1, Pagaila discloses a package (for example, Fig. 11b) with embedded traces (214, 216) comprising: a main body (referred to as “A” by examiner’s annotation shown in fig. 11b below) comprising: an insulating body (204); and a die (124) and multiple conductive traces (conductive layers 132 functioning as conductive traces) mounted in the insulating body (204), wherein the die (124) is electrically connected to the multiple conductive traces (132); and multiple leads (222a, 222b, 222c) extending outward from the main body (A), and each of the multiple leads (222a, 222b, 222c) comprising: a lead carrier (a lead 222b; or 222b, 222a; or 222a, 222b, 222c functioning as a lead carrier) integrally extending (as shown in fig. 11b) from the insulating body (A) and having two opposite surfaces (the bottom and top surfaces); and first and second conducting layers (216, 226) formed on the two opposite surfaces (the bottom and top surfaces) of the lead carrier (222b) respectively and electrically connected to one of the multiple conductive traces (132) so that the first and second conducting layers (216, 226) of each lead are electrically connected to the die (124), wherein the first conducting layer (216) of each lead (a lead 222b; or 222b, 222a; or 222a, 222b, 222c) is embedded in the lead carrier (222b; or 222b, 222a; or 222a, 222b, 222c). PNG media_image1.png 390 776 media_image1.png Greyscale Pagaila does not clearly disclose each of the multiple leads, two gaps are respectively disposed at two sides of each lead carrier, and each gap is formed between one side edge of the lead carrier and one side edge of the first conducting layer. However, Hsu discloses each of the multiple leads (referred to as “210A” by examiner’s annotation shown in fig. 3 below), two gaps (228) are respectively disposed at two sides (inner sides) of each lead carrier (210), and each gap (228) is formed between one side edge (sidewall edge 232) of the lead carrier (210) and one side edge of the first conducting layer (230). (for example, see fig. 3). PNG media_image2.png 409 734 media_image2.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Pagaila’s device to have each of the multiple leads, two gaps are respectively disposed at two sides of each lead carrier, and each gap is formed between one side edge of the lead carrier and one side edge of the first conducting layer as taught by Hsu in order to minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art. With regard to claim 2, Pagaila discloses the second conducting layers (226) has two side edges (referred to as “226A” by examiner’s annotation shown in fig. 11b below) respectively aligning with the two side edges (222b1) of the lead carrier (222b). PNG media_image3.png 460 866 media_image3.png Greyscale With regard to claim 3, Hsu discloses each of the multiple leads (210A), the second conducting layer (referred to as “230B” by examiner’s annotation shown in fig. 3 below) is also embedded in the lead carrier (210), and another two gaps (referred to as “228B” by examiner’s annotation shown in fig. 3 below) are respectively disposed at the two sides (inner sides) of each lead carrier (210A), and each of the another two gaps (228B) is formed between the one side edge (inner side edge) of the lead carrier and one side edge of the second conducting layer (230B). PNG media_image4.png 494 744 media_image4.png Greyscale With regard to claim 4, Hsu discloses the first conducting layer (230) has a surface being coplanar with and exposed from a bottom surface of the lead carrier (210), and has a trace width (referred to as “X1” by examiner’s annotation shown in fig. 3 below) being smaller than a width (referred to as “X2” by examiner’s annotation shown in fig. 3 below) of the lead carrier. PNG media_image5.png 426 647 media_image5.png Greyscale With regard to claim 5, Pagaila discloses the multiple leads (222a, 222b, 222c) extend outward from a same side (a bottom side) of the main body (A). With regard to claims 6, 7, 10, Pagaila discloses the first and second conducting layers (216, 226) of each lead are electrically connected to each other through a conductive via (a conductive layer 314, forming a via or hole of the insulation body, functioning as a conductive via) formed in the main body (A). With regard to claims 8, 9, Pagaila discloses the first and second conducting layers (216, 226) of each lead are electrically connected to each other through a conductive via (a conductive layer 314, or 314, 222b functioning as a conductive via) formed in the main body (A); or through a conductive via (a conductive layer 228a functioning as a conductive via) formed in (in vertical view) the main body (A). Response to Amendment 5. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Conclusion 6. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. 7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TAN N TRAN/ Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Aug 24, 2023
Application Filed
Oct 16, 2025
Non-Final Rejection — §103
Feb 13, 2026
Response Filed
Mar 06, 2026
Final Rejection — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
86%
Grant Probability
97%
With Interview (+10.2%)
2y 3m
Median Time to Grant
Moderate
PTA Risk
Based on 1088 resolved cases by this examiner. Grant probability derived from career allow rate.

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