Prosecution Insights
Last updated: July 17, 2026
Application No. 18/455,211

REDUCED RESIDUE AT ETCHED STRUCTURE SIDEWALLS

Final Rejection §102§103
Filed
Aug 24, 2023
Examiner
MCDONALD, JASON ANDREW
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
50%
Grant Probability
Moderate
3-4
OA Rounds
5m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 50% of resolved cases
50%
Career Allowance Rate
2 granted / 4 resolved
-18.0% vs TC avg
Strong +100% interview lift
Without
With
+100.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
41 currently pending
Career history
57
Total Applications
across all art units

Statute-Specific Performance

§103
93.1%
+53.1% vs TC avg
§102
4.3%
-35.7% vs TC avg
§112
2.1%
-37.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 4 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Status The examiner acknowledges amendments to claims 1-4, 9-10, and 21-23 in the reply dated 8 April 2026. Claims 17-20 were previously cancelled. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 9-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al (US 20210134982 A1, hereinafter “Lin”). Regarding Claim 9 – Lin discloses a method comprising: forming a first fin structure and a second fin structure (64A and 64B [0024] and Fig. 4); forming an isolation region (62 [0026]) between the first fin structure and the second fin structure ([0026] and Fig. 4); recessing the isolation region ([0028] and Fig. 4); depositing a sacrificial gate material (68 [0033]) over the recessed surface of the isolation region (Fig. 5A); and etching a portion of the sacrificial gate material to form a sacrificial gate ([0035]), recessing the isolation region ([0071]) to provide the isolation region with a recessed surface, the wave shape including a first terminal crest (1st Term. Fig. 19C), a second terminal crest (2nd Term. Fig. 19C), and an intermediate crest between the first terminal crest and the second terminal crest (1st Int. Fig. 19C), wherein the first terminal crest and the second terminal crest have a greater height than the intermediate crest (Fig. 19C). Lin fails to expressly disclose recessing the isolation region to provide the isolation region with a recessed surface having a wave shape before depositing the sacrificial gate material. However, Lin teaches the top surface of the isolation region between fin structures may have a concave shape ([0028] and Fig. 19A). Lin teaches further that the curved, concave shape may in fact be wavy or serrated, as shown in Figure 19C. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention that a recessed isolation surface between fin structures may have a wavy or serrated shape prior to deposition of sacrificial gate material. PNG media_image1.png 345 433 media_image1.png Greyscale PNG media_image2.png 458 480 media_image2.png Greyscale PNG media_image3.png 610 579 media_image3.png Greyscale Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (US 20210134982 A1, hereinafter “Lin”), in view of the following arguments. Regarding Claim 15 – Lin discloses all the limitations of claim 9. Lin further discloses the first fin structure has a sidewall (Sidewall in Fig. 19C); an angle is defined between the sidewall and the recessed surface (Angle in Fig. 19C). Lin fails to explicitly disclose the angle is from 120 to 160 degrees. However, Lin discloses the angle is greater than 90 and less than 180 degrees. This is clear in Figure 19C, and presents an overlapping range and a prima facie case of obviousness (MPEP 2144.05(I)). Regarding Claim 16 – Lin discloses all the limitations of claim 9. Lin fails to explicitly disclose recessing the isolation region to provide the isolation region with the recessed surface having the wave shape comprises performing an etch process using an etchant gas selected from NH3, NF3, HBr, and H2; using a passivation gas selected from N2 and 02; and using a dilute gas selected from He, Ar, and N2, at a power of from 10 to 4000 Watts; at a pressure of from 10 mTorr to 3 Torr; and with a gas flow of from 20 to 3000 sccm. However, Lin discloses recessing the isolation region to provide the isolation region with the recessed surface having the wave shape comprises performing an etch process using an etchant gas selected from HBr and H2 ([0056]); using a passivation gas selected from N2 and 02 ([0056]); and using a dilute gas selected from He and Ar ([0056]) at a power of from 10 to 3000 Watts ([0057]); at a pressure of from 1 mTorr to 800 mTorr; and with a gas flow of from 10 to 5000 sccm. The gases in the prior art are from the same groups as the instant application, and the ranges in the prior art all overlap with the claimed ranges, presenting a prima facie case of obviousness. See MPEP 2144.05(I). Claims 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20230395660 A1, hereinafter “Kim”), in view of Frougier et al (US 20240128346 A1, hereinafter “Frougier”). Regarding Claim 21 – Kim discloses a method comprising: forming a first source/drain region and a second source/drain region distanced from the first source/drain region in a lateral X-direction (multiple source/drain regions [0008] and Fig. 2A); forming a first dielectric region (118b [0061] and 1st 118b in Fig. 2C); forming a fin structure including a semiconductor nanosheet (NSS [0024] and Fig. 2A) distanced from a mesa portion in a vertical Z-direction (Fig. 2A), wherein the semiconductor nanosheet extends in the lateral X-direction from the first source/drain region to the second source/drain region (between Source/Drain Regions in Fig. 2A); forming a gate structure (160 [0059] and Fig. 2A) overlying the fin structure (Fig. 2A), wherein the gate structure includes a metal gate and a high-k gate dielectric ([0059]), wherein the gate structure extends in a longitudinal Y- direction (Fig. 2C), and wherein a lowest portion of the gate structure is located between the mesa portion and the semiconductor nanosheet (Fig. 2A); forming an inner spacer (132 [0035] and Fig. 2A) separating the first source/drain region from the lowest portion of the gate structure in the lateral X-direction (Figs. 2A and 2C); and forming a spacer structure (118a [0061] and Fig. 2C)) separating the dielectric region from the gate structure in the lateral X-direction (Fig. 2C); wherein a minimum distance between the spacer structure and the inner spacer in the longitudinal Y-direction is from 0 to 2 nanometers (nm) (appears to be 0 nm in Fig. 2C). Kim fails to disclose the inner spacers are formed of dielectric material. However, Frougier discloses the inner spacers are formed of dielectric material (28 [0060]). Frougier discloses an analogous nanosheet FET structure to Kim. Frougier teaches forming inner spacers of dielectric material for the benefit of protecting the nanosheets from thinning (Frougier [0067]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Kim and Frougier to form inner spacers of dielectric material for the benefit of protecting the nanosheets from thinning. PNG media_image4.png 548 546 media_image4.png Greyscale PNG media_image5.png 420 452 media_image5.png Greyscale Regarding Claim 22 – Kim modified by Frougier discloses all the limitations of claim 21. The combination of Kim and Frougier further discloses the minimum distance is located at an interface, wherein the metal gate extends toward the interface to an edge, and wherein a lateral profile of the edge of the metal gate has an internal angle of greater than 100 degrees (A1 in annotated Fig. 2C is greater than 100 degrees). Regarding Claim 23 – Kim modified by Frougier discloses all the limitations of claim 21. The combination of Kim and Frougier further discloses the minimum distance is located at an interface, wherein the metal gate extends toward the interface to an edge, and wherein a lateral profile of the edge of the metal gate has an internal angle of from 100 to 120 degrees (A1 in annotated Fig. 2C between 100 and 180 degrees, presenting an overlapping range and prima facie case of obviousness. See MPEP 2144.05(I)). Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20230395660 A1, hereinafter “Kim”), in view of Frougier et al (US 20240128346 A1, hereinafter “Frougier”), and further in view of Lin et al (US 20210134982 A1, hereinafter “Lin”). Regarding Claim 24 – Kim modified by Frougier discloses all the limitations of claim 21. The combination of Kim and Frougier further discloses forming a first shallow isolation region (114 [0026] and 1st in annotated Fig. 1) distanced from a second shallow isolation region (2nd in annotated Fig. 1) in the longitudinal Y-direction; wherein: the mesa portion of the fin structure (FA [0024] and Fig. 1) is located between the first shallow isolation region and the second shallow isolation region (Fig. 1). Kim fails to disclose the mesa portion of the fin structure has a sidewall abutting the first shallow isolation region; the first shallow isolation region has an uppermost surface; an angle is defined between the sidewall and the uppermost surface; and the angle is from 120 to 160 degrees. However, Lin discloses the mesa portion (64, Lin [0019] and Fig. 1) of the fin structure has a sidewall abutting the first shallow isolation region (62, Lin [0019] and Fig. 1); the first shallow isolation region has an uppermost surface (62U, Lin [0060] and Fig. 14A); an angle (A2, annotated Lin Fig. 14A) is defined between the sidewall and the uppermost surface (shown in Fig. 14A as orthogonal view to Fig. 1); and the angle is between 90 and 180 degrees (Fig. 14A), presenting a prima facie case of obviousness. See MPEP 2144.05(I). Kim and Lin both describe finFET devices. Although Kim describes a shallow isolation region between fins, a cross section is not shown with the fins having isolation between them. Lin shows a typical cross section of fins with isolation between them (Lin [0024] and Fig. 4) and a later recess after etching back the sacrificial gate (Lin [0066] and Fig. 14A). This is simply not shown in Kim, but is commonly known in the industry. Setting the angle between the sidewall and the surface of the isolation where it meets the sidewall is a case of routine optimization. See MPEP 2144.05(II)(A). PNG media_image6.png 445 468 media_image6.png Greyscale PNG media_image7.png 329 274 media_image7.png Greyscale Allowable Subject Matter Claims 1-8 are allowed. The following is a statement of reasons for the indication of allowable subject matter: It appears the prior art of record known to the examiner, either alone or in combination, fails to disclose “the residue does not contact the second layer” as defined in claim 1. The closest prior art discloses the presence of residue at the base of vertical features, preventing the residue, and removing the residue, but not that the residue does not contact a second layer as defined in claim 1. Chang (US 20230352546 A1) teaches “...plasma treatment is performed to remove etching residues or intermixed materials left from the removal of the cladding layers” ([0051]), but is silent with respect to residue remaining on a sidewall below and not touching the second layer in a stack over a device mesa portion. Voronin (US 20200273992 A1) teaches: “...improving the verticality of etch profiles may be achieved at the expense of un-etched residues at the bottom of the feature being formed” ([0003]), but is silent with respect to residue remaining on a sidewall below and not touching the second layer in a stack over a device mesa portion. Tsai (US 20200075748 A1) teaches: “...it is found that some polysilicon may remain over corners between the polysilicon gate and the fin structure, and the polysilicon residue, known as the “footing”, of the sacrificial gate layer may cause metal extrusion issues” ([0020]), but is silent with respect to residue remaining on a sidewall below and not touching the second layer in a stack over a device mesa portion. Claims 10-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claim 10 describes the first and second terminal crests abutting the first and second fin structures, respectively. This appears to be orthogonal in the X-Y plane to the orientation of a similar feature in the prior art. Claims 11-14 are objected to because of their dependency on claim 10. Response to Arguments Applicant argues the orientation of the claimed wave shape is orthogonal to that of the prior art. However, the claim language does not reflect this position. Further, a wavy recess of the isolation region prior to sacrificial gate material deposition is within reasonable interpretation of the prior art. Therefore, claim 9 is rejected as explained above. Applicant’s further arguments have been considered but are moot in view of the new grounds of rejection necessitated by amendment. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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Prosecution Timeline

Aug 24, 2023
Application Filed
Apr 05, 2024
Response after Non-Final Action
Dec 31, 2025
Non-Final Rejection mailed — §102, §103
Feb 10, 2026
Interview Requested
Mar 04, 2026
Examiner Interview Summary
Mar 04, 2026
Applicant Interview (Telephonic)
Apr 08, 2026
Response Filed
Jun 04, 2026
Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Patent 12666616
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
3y 5m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 1 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
50%
Grant Probability
99%
With Interview (+100.0%)
3y 3m (~5m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 4 resolved cases by this examiner. Grant probability derived from career allowance rate.

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