DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The rejection as set forth in the office action mailed 4 June 2026 is withdrawn in view of the remarks filed 10 August 2026. A new rejection is provided herein below.
Claim Status
Claims 17-20 were previously cancelled.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 630 in Figure 3. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al (US 20220052046 A1, hereinafter “Choi”), in view of Yeung et al (US 9,842,914 B1, hereinafter “Yeung”).
Regarding Claim 21 – Choi discloses a method comprising: forming a first source/drain region and a second source/drain region distanced from the first source/drain region in a lateral X-direction ([0037] and Fig. 2D); forming a dielectric region (144 [0068] and Fig. 2A); forming a fin structure including a semiconductor nanosheet (FA [0029] and Figs. 2A and 2D) distanced from a mesa portion in a vertical Z-direction (Fig. 2A), wherein the semiconductor nanosheet extends in the lateral X-direction from the first source/drain region to the second source/drain region (between Source/Drain Regions 130 [0037] and Fig. 2A); forming a gate structure (160 [0032] and Fig. 2A) overlying the fin structure (Fig. 2A), wherein the gate structure includes a metal gate and a high-k gate dielectric ([0051-0052]), wherein the gate structure extends in a longitudinal Y- direction (Fig. 2D), and wherein a lowest portion of the gate structure is located between the mesa portion and the semiconductor nanosheet (Fig. 2A); forming an inner spacer (132 [0039] and Fig. 2A) separating the first source/drain region from the lowest portion of the gate structure in the lateral X-direction (Figs. 2A and 2D); and forming a spacer structure (118 [0061] and Fig. 2D) separating the dielectric region from the gate structure in the lateral X-direction (Fig. 2D); wherein a minimum distance between the spacer structure and the inner spacer in the longitudinal Y-direction is from 0 to 2 nanometers (nm) (118 and 132 shown in direct contact in Fig. 2D).
Choi fails to disclose the inner spacers are formed of dielectric material.
However, Yeung discloses the inner spacers are formed of dielectric material (1600, col. 9, lines 50-58 and Fig. 18).
Yeung discloses an analogous nanosheet FET structure to Choi. Yeung teaches forming inner spacers of dielectric material for the benefit of reducing parasitic overlap capacitance between the gate and the source/drain epitaxy regions (Yeung col. 6, lines 21-23). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Choi and Yeung to form inner spacers of dielectric material for the benefit of reducing parasitic overlap capacitance between the gate and the source/drain epitaxy regions.
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Regarding Claim 22 – Choi modified by Yeung discloses all the limitations of claim 21.
The combination of Choi and Yeung further discloses the minimum distance is located at an interface, wherein the metal gate extends toward the interface to an edge, and wherein a lateral profile of the edge of the metal gate has an internal angle of greater than 100 degrees (A1 in annotated Choi Fig. 2D greater than 90°, presenting an overlapping range and prima facie case of obviousness. See MPEP 2144.05(I)).
Regarding Claim 23 – Choi modified by Yeung discloses all the limitations of claim 21.
The combination of Choi and Yeung further discloses the minimum distance is located at an interface, wherein the metal gate extends toward the interface to an edge, and wherein a lateral profile of the edge of the metal gate has an internal angle of from 100 to 120 degrees (A1 in annotated Choi Fig. 2D between 90° and 180°, presenting an overlapping range and prima facie case of obviousness. See MPEP 2144.05(I)).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al (US 20220052046 A1, hereinafter “Choi”), in view of Yeung et al (US 9,842,914 B1, hereinafter “Yeung”), and further in view of Lin et al (US 20210134982 A1, hereinafter “Lin”).
Regarding Claim 24 – Choi modified by Yeung discloses all the limitations of claim 21.
The combination of Choi and Yeung further discloses forming a first shallow isolation region (114 Choi [0031] and 1st in annotated Choi Fig. 1) distanced from a second shallow isolation region (2nd in annotated Choi Fig. 1) in the longitudinal Y-direction; wherein: the mesa portion of the fin structure (FA, Choi [0024] and Fig. 1) is located between the first shallow isolation region and the second shallow isolation region (Choi Fig. 1).
Choi fails to disclose the mesa portion of the fin structure has a sidewall abutting the first shallow isolation region; the first shallow isolation region has an uppermost surface; an angle is defined between the sidewall and the uppermost surface; and the angle is from 120 to 160 degrees.
However, Lin discloses the mesa portion (64, Lin [0019] and Fig. 1) of the fin structure has a sidewall abutting the first shallow isolation region (62, Lin [0019] and Fig. 1); the first shallow isolation region has an uppermost surface (62U, Lin [0060] and Fig. 14A); an angle is defined between the sidewall and the uppermost surface (A2, annotated Lin Fig. 14A); and the angle is between 90° and 180° (as shown in Fig. 14A, which must be the case with a concave profile as described by Lin in [0060], which is an overlapping range of the claimed 120° to 160°, presenting a prima facie case of obviousness. See MPEP 2144.05(I)).
Choi and Lin both describe finFET devices. Although Choi describes a shallow isolation region between fins, a cross section is not shown with the fins having isolation between them. Lin shows a typical cross section of fins with isolation between them (62, Lin [0024] and Fig. 4) and a later recess after etching back the sacrificial gate, including a concave shape of the top surface (62U, Lin [0060] and Fig. 14A), causing the angle between the sidewall and uppermost surface to be greater than 90°. The same angle must be less than 180° for material to span the space between mesa portions. This is simply not shown in Choi, but is commonly known in the industry. The angle between the sidewall and the surface of the isolation where it meets the sidewall is therefore inherently between a right angle (90°) and a straight line (180°), which is an overlapping range and a prima facie case of obviousness. See MPEP 2112(II) and 2144.05(I).
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Allowable Subject Matter
Claims 1-8 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: It appears the prior art of record known to the examiner, either alone or in combination, fails to disclose “the residue does not contact the second layer” as defined in claim 1. The closest prior art discloses the presence of residue at the base of vertical features, preventing the residue, and removing the residue, but not that the residue does not contact a second layer as defined in claim 1.
Chang et al (US 20230352546 A1) teaches “...plasma treatment is performed to remove etching residues or intermixed materials left from the removal of the cladding layers” ([0051]), but is silent with respect to residue remaining on a sidewall below and not touching the second layer in a stack over a device mesa portion.
Voronin et al (US 20200273992 A1) teaches: “...improving the verticality of etch profiles may be achieved at the expense of un-etched residues at the bottom of the feature being formed” ([0003]), but is silent with respect to residue remaining on a sidewall below and not touching the second layer in a stack over a device mesa portion.
Tsai et al (US 20200075748 A1) teaches: “...it is found that some polysilicon may remain over corners between the polysilicon gate and the fin structure, and the polysilicon residue, known as the “footing”, of the sacrificial gate layer may cause metal extrusion issues” ([0020]), but is silent with respect to residue remaining on a sidewall below and not touching the second layer in a stack over a device mesa portion.
Claims 2-8 are allowable for their dependency on claim 1.
Claims 9-16 are allowed.
It appears the prior art of record known to the examiner, either alone or in combination, fails to disclose the sequence of “...recessing the isolation region to provide the isolation region with a recessed surface having a wave shape, the wave shape including a first terminal crest, a second terminal crest, and an intermediate crest between the first terminal crest and the second terminal crest, wherein the first terminal crest and the second terminal crest have a greater height than the intermediate crest; depositing a sacrificial gate material over the recessed surface of the isolation region...” as recited in claim 9. The closest prior art discloses recessing the isolation to provide the isolation region with a recessed surface having a potentially wave shape, but only after removal of the sacrificial gate material.
Lin et al (US 20210134982 A1) teaches “...the second etching process is performed to remove portions of the gate fill material...” and “...a center area of the upper surface of the isolation regions 62, which is exposed by the recess 88, has a curved (e.g., concave) upper surface...” and shown with a wave shape in Fig. 19C. The concave recess is only mentioned being formed after removal of the sacrificial gate material, and only described as having a wave shape in the figure.
Duriez et al (US 9,711,608 B1) teaches “the insulating material layer 41 is recessed to form an isolation insulating layer 40 so that the upper portions of the fin structures 30 are exposed” and Figure 5 appears to show the insulating material surface recessed in a concave shape, but no mention is made of forming a wave shape.
Huang et al (US 20210134794 A1) teaches “...a vertical, dry etch, may be performed to remove portions of the dielectric material surrounding the first, second, and third stacks of semiconductor layers 601, 603, 605 to form the lower isolation structure 110a. It will be appreciated that other processes and/or order of steps to form the lower isolation structure 110a are also within the scope of the disclosure.” The surface of the lower isolation structure thus formed is shown with a wave shape in Figure 15, but not matching the claimed profile and not explained by Huang.
Claims 10-16 are allowable for their dependency on claim 1.
Response to Arguments
The applicant argues that claim 9 requires the wave-shaped recessed surface of the isolation region to exist before the sacrificial gate material is deposited, and the process sequence in the reference results in a recess only after sacrificial gate material is removed. This argument appears persuasive, and claim 9 and its dependent claims have been added to the allowable subject matter section of this office action as explained above. Arguments regarding the rejections of claims 15 and 16 are moot in view of the allowance of the independent claim upon which they depend.
Applicant argues the angle specified in claim 24 is covered under the clause in Lin [0004] that “various features are not drawn to scale”. However, regardless of scale in the figures, the angle must be in the 90°-180° range, as explained above. Lin Figure 14A shows the angle in this range, but it is not necessary to rely on the figure alone.
Applicant’s arguments with respect to claims 21-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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