DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to amended claims 14-33 are considered persuasive. However, since amendments to the claims have been made, further examination is necessary. The amended claims are found to be rendered obvious by new prior art, so the rejection of claims 14-33 is maintained. As seen below, independent claims 14 and 21 are now rejected by Frougier et al. US 20230178544 in view of Chang et al. US 20220344483 and claim 28 is rejected by Frougier et al. US 20230178544 in view of Pan et al. US 20230369327.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 14-24, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Frougier et al. US 20230178544 in view of Chang et al. US 20220344483.
Regarding claim 14, Frougier discloses a method for forming a semiconductor structure, comprising:
forming a nanosheet stack fin over a substrate (described in paragraph [0064] and illustrated by figure 2, where the nanosheet stacks are formed over the substrate 110)
forming isolation structures at two sides of the nanosheet stack fin (figure 2, 210, [0065]);
forming a sacrificial gate structure over the nanosheet stack fin (formation of a dummy
gate structure is described in paragraph [0066] and shown in figure 3),
wherein the nanosheet stack fin extends in a first direction, and the sacrificial gate structure extends in a second direction different from the first direction (figure 1A shows
that nano stack sheets 14 extend in the X direction and gate dummy structures 12 extend
in the perpendicular direction Y);
forming a first dielectric layer over the sacrificial gate structure and the nanosheet stack fin (figure 5, 310/320 comprise a first dielectric layer over the sacrificial gate structure and the nanosheet stack fin),
forming a second dielectric layer over the first dielectric layer (figure 5, 310/320);
removing portions of the second dielectric layer to expose portions of the first dielectric layer (310/320) over the sacrificial gate structure ([0070]);
removing portions of the first dielectric layer (figure 6, 410) and portions of the nanosheet stack fin at two sides of the sacrificial gate structure to form a plurality of recesses (figure 6 and described in paragraph [0070]);
and forming epitaxial source/drain structures in the recesses (figure 7, 730, described in paragraph [0077]).
Frougier lacks wherein the first dielectric layer covers sidewalls and a top of the sacrificial gate structure;
However, Chang discloses a method for forming a similar semiconductor structure, wherein the first dielectric layer covers sidewalls and a top of the sacrificial gate structure (first dielectric structure 216 in figures 6A and 6B covers the sidewalls and tops of the sacrificial gate structure 214 [0018]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the time of filing to extend the dielectric sidewall layers of Frougier to cover the sidewalls and tops of the sacrificial gate structure in order to better protect the sacrificial gate structure during subsequent steps in the formation of the semiconductor structure.
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Regarding claim 15, Frougier as modified by Chang discloses the method of claim 14, wherein the removing of the portions of the second dielectric layer further comprises: performing a planarization on the second dielectric layer (figure 6, 410) such that a top surface of the second dielectric layer (310/320) and a first top surface of the first dielectric layer (410) over the sacrificial gate structure is level (See annotated figure 6, where the top surfaces of first dielectric layer 310/320 and second dielectric layer 410 are planarized to be level over the dummy gate structure); and performing a first etch-back operation (described in paragraphs [0071-0072]) on the second dielectric layer (figure 7, 410) to expose portions of the first dielectric layer (310/320) over the sacrificial gate structure.
Regarding claim 16, Frougier as modified by Chang discloses the method of claim 15, wherein the top surface of the second dielectric layer (410) is lowered to level with a second top surface of the first dielectric layer (310/320) over the nanosheet stack fin after the first etch-back
operation (see annotated figure 6 above, [0070])
Regarding claim 17, Frougier as modified by Chang discloses the method of claim 14, further comprising performing a second etch-back to remove a portion of the first dielectric layer over the sacrificial gate structure to form a spacer at sidewalls of the sacrificial gate structure. (See figure 6, where layer 310/320 is removed and spacer 610 is formed at the sidewalls of the dummy gate structure, as described in paragraph [0070]).
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Regarding claim 18, Frougier as modified by Chang discloses the method of claim 14, wherein bottom surfaces of the recesses are lower than a bottom surface of the first dielectric layer. (It is evident from annotated figure 6', that the bottom surfaces of the recesses are lower than bottom surfaces 310/320 of the first dielectric layer.)
Regarding claim 19, Frougier as modified by Chang discloses the method of claim 14, further comprising forming inner spacers prior to the forming of the epitaxial source/drain structures (Figures 6 and 7 disclose sequential steps for the formation of the inner spacers shown in figure 6, 610 and described in paragraph [0070] and the subsequent epitaxial growth of source/drain regions, described in paragraph [0074] and illustrated in figure 7, 710).
Regarding claim 20, Frougier as modified by Chang discloses the method of claim 14, further comprising replacing the sacrificial gate structure with a metal gate structure. (figure 9 illustrates the selective removal of the dummy gate material [0078], while figure 15 illustrates the device following the formation of the metal gate stack structure [0086]).
Regarding claim 21, Frougier discloses the method for forming a semiconductor structure, comprising:
forming a nanosheet stack fin over a substrate (described in paragraph [0064] and
illustrated by figure 2, where the nanosheet stacks are formed over the substrate 110);
forming isolation structures at two sides of the nanosheet stack fin (figure 2, 210, [0065]);
forming a sacrificial gate structure over the nanosheet stack fin (formation of a dummy
gate structure is described in paragraph [0066] and shown in figure 3), wherein
the nanosheet stack fin extends in a first direction, and the sacrificial gate structure
extends in a second direction different from the first direction (Figure 1A shows that
nano stack sheets 14 extend in the X direction and gate dummy structures 12 extend in the perpendicular direction Y.);
forming a first dielectric layer over the sacrificial gate structure and the nanosheet stack
fin (figure 3, 310/320 is a dielectric layer [0066] formed over the dummy gate structure
and the nano stack fin);
forming a second dielectric layer (figure 5, 410, [0069]) over the first dielectric layer (figure 5, 310/320);
removing portions of the second dielectric layer (figure 6, 410) to expose portions of the first dielectric layer (figure 5, 310/320) over the sacrificial gate structure [0070];
removing portions of the first dielectric layer (figure 6, 410) to form a spacer (See figure 6, where layer 310/320 is removed and spacer 610 is formed at the sidewalls of the dummy gate structure, as described in paragraph [0070]);
removing portions of the nanosheet stack fin at two sides of the sacrificial gate structure to form a plurality of recesses (figure 6 and described in paragraph [0070]),
and forming epitaxial source/drain structures in the recesses (Figure 7 shows the source/drain regions (710), which were grown epitaxially in the recesses as described in paragraph [0074].).
Frougier lacks wherein bottoms of the recesses are lower than top surfaces of the isolation structures, and the isolation structures are covered by the first dielectric layer.
However, Chang et al. discloses wherein bottoms of the recesses (the recesses comprising 238 in figure 12A) are lower than top surfaces of the isolation structures (isolation structures 212/212t are shown in figure 12C, which is a perpendicular view corresponding to the structure of 12A), and the bottoms of these recesses are lower than the top surface of isolation structure (as can be seen by comparing the position of these features in figures 12A and 12C relative to the level of the substrate layer 202), and the isolation structures (figure 12C 212/212t) are covered by the first dielectric layer (216f, a portion of first dielectric layer 216).
Therefore, it would have been obvious to a person having ordinary skill in the art before the time of filing to deepen the recesses of Frougier to be lower than the tops of the isolation layer in order to improve performance by reducing parasitic resistance and enhancing drive current.
Regarding claim 22, Frougier as modified by Chang discloses the method of claim 21, wherein the removing of the portions of the second dielectric layer further comprises:
performing a planarization on the second dielectric layer such that a top surface of the second dielectric layer and a first top surface of the first dielectric layer over the sacrificial gate structure are level (See annotated figure 6, where the top surfaces of first dielectric layer 310/320 and second dielectric layer 410 are planarized to be level over the dummy gate structure); and
performing a first etch-back operation [0070] on the second dielectric layer (figure 6, 410) to expose portions of the first dielectric layer (figure 6, 310/320) over the sacrificial gate structure (illustrated in figure 6).
Regarding claim 23, Frougier as modified by Chang discloses the method of Claim 22, wherein the top surface of the second dielectric layer (figure 6, 410) is lowered to level with a second top surface of the first dielectric layer (figure 6, 310/320) over the nanosheet stack fin after the first etch-back operation (This is illustrated annotated figure 6, see the rejection of claim 16 above.)
Regarding claim 24, Frougier as modified by Chang discloses the method of claim 21, further comprising performing a second etch-back to remove a portion of the first dielectric layer over the sacrificial gate structure to form the spacer. (See figure 6, where layer 310/320 is removed and spacer 610 is formed at the sidewalls of the dummy gate structure, as described in paragraph [0070]).
Regarding claim 27, Frougier as modified by Chang discloses the method of claim 21, further comprising replacing the sacrificial gate structure with a metal gate (Figure 7 shows the source/drain regions (710), grow epitaxially in the recesses as described in paragraph [0074].)
Claims 25 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Frougier in view of Chang as applied to claim 21 above, and further in view of Glass et al. US 11769836.
Regarding claim 25, Frougier as modified by Chang discloses the method of claim 21, further comprising forming an etch stop layer over the epitaxial source/drain structure and the second dielectric layer (Figure 10 illustrates the protective layer 1010, described in paragraphs [0081] and [0086]), deposited on the nanosheet channels (comprising the source/drain structure) and the gate sidewalls (comprising the second dielectric layer 410).
Frougier as modified by Chang lacks the etch stop layer being formed over a remaining portion of the first dielectric layer (310/320).
However, Glass discloses a similar device, in which the first dielectric layer as disclosed in Frougier as modified by Chang also comprises a relaxed buffer layer part composed of the same material. In Glass, figure 2, the first dielectric layer comprises dielectric relaxed buffer layer 126 [0025], which remains after other portions of the first dielectric layer are removed. Thus, the etch stop layer (layer 174, a contact barrier layer, which can function as an etch stop) is deposited over the remaining portion of the first dielectric layer.
Therefore, it would have been obvious to a person of ordinary skill in the art before the time of filing to configure the first dielectric layer of Frougier as modified by Chang as in Glass to incorporate a relaxed buffer in order to improve structural quality (Moutanabbir et al.).
Regarding claim 26, Frougier as modified Chang and further in view of Glass discloses the method of claim 25, wherein the etch stop layer is coupled to the first dielectric layer and the second dielectric layer. Figure 13 of Frougier illustrates that the etch stop layer 1010 is physically connected to the second dielectric layer (410). The first dielectric layer of Glass, as discussed in the rejection of claim 25, is also coupled to the etch stop layer physically, as it is in physical contact with that layer. See Glass figure 2, where the remaining part of first dielectric layer (126) is physically connected to the etch stop layer (174).
Claims 28-33 are rejected under 35 U.S.C. 103 as being unpatentable over Frougier et al. US 20230178544 in view of Pan et al. US 20230369327.
The applied reference has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Regarding claim 28, Frougier discloses a method for forming a semiconductor structure,
comprising:
forming a nanosheet stack fin over a substrate (described in paragraph [0064] and
illustrated by figure 2, where the nanosheet stacks are formed over the substrate 110);
forming isolation structures at two sides of the nanosheet stack fin (figure 2, 210, [0065]);
forming a sacrificial gate structure over the nanosheet stack fin (formation of a dummy
gate structure is described in paragraph [0066] and shown in figure 3), wherein
the nanosheet stack fin extends in a first direction, and the sacrificial gate structure
extends in a second direction different from the first direction (figure 1A shows that
nano stack sheets 14 extend in the X direction and gate dummy structures 12 extend in the perpendicular direction Y);
forming a first dielectric layer over the sacrificial gate structure and the nanosheet stack
fin (figure 3, 310/320 is a dielectric layer [0066] formed over the dummy gate structure
and the nano stack fin);
forming a second dielectric layer (figure 5, 410, [0069]) over the first dielectric layer;
removing portions of the second dielectric layer (figure 6, 410) to expose portions of the first dielectric layer (310/320) over the sacrificial gate structure [0070];
removing portions of the first dielectric layer and portions of the nanosheet stack fin at two sides of the sacrificial gate structure to form a plurality of recesses (figure 6 and described in paragraph [0070]); and
the isolation structure is covered by the first dielectric layer and the second dielectric layer (see the rejection of this identical limitation in claim 21);
removing the second dielectric layer to expose the first dielectric layer (The sequence of figure 5 and figure 6 illustrates that the second dielectric layer (410) was removed to expose the first dielectric layer (310/320) in the direction orthogonal to X and Y); and
forming epitaxial source/drain structures in the recesses. (Figure 7 shows the source/drain regions (710), which were grown epitaxially in the recesses as described in paragraph [0074].)
Frougier lacks wherein topmost surfaces of the epitaxial source/drain structures are higher than a topmost surface of the first dielectric layer.
However, Pan discloses an embodiment of a comparable semiconductor device wherein topmost surfaces of the epitaxial source/drain structures are higher than a topmost surface of the first dielectric layer. In the embodiment of figure 12, the first dielectric layer 55L, seen in figure 10, is partially removed, leaving residual first dielectric layer 55F, wherein the topmost layer of the epitaxial source/drain 80N/80P is higher than the residual part of the first dielectric layer 55f.
Therefore, it would have been obvious to a person having ordinary skill in the art to leave a residual layer of the first dielectric layer in a position lower than the topmost layer of the source/drain region to enhance structural stability.
Regarding claim 29, Frougier as modified by Pan discloses the method of claim 28, wherein the removing of the portions of the second dielectric layer further comprises:
performing a planarization on the second dielectric layer such that a top surface of the second dielectric layer and a first top surface of the first dielectric layer over the sacrificial gate structure are level (See annotated figure 6, where the top surfaces of first dielectric layer 310/320 and second dielectric layer 410 are planarized to be level over the dummy gate structure); and
performing a first etch-back operation [0070] on the second dielectric layer (figure 6. 410) to expose portions of the first dielectric layer (figure 6, 310/320) over the sacrificial gate structure (illustrated in figure 6)
Regarding claim 30, Frougier as modified by Pan discloses the method of claim 29, wherein the top surface of the second dielectric layer (figure 6, 410) is lowered to level with a second top surface of the first dielectric layer (figure 6, 310/320) over the nanosheet stack fin after the first etch-back operation (This is illustrated annotated figure 6, see the rejection of claim 16 above.)
Regarding claim 31, Frougier as modified by Pan discloses the method of claim 29, further comprising performing a second etch-back to remove a portion of the first dielectric layer over the sacrificial gate structure to form a spacer over sidewalls of the sacrificial gate structure. (See figure 6, where layer 310/320 is removed and spacer 610 is formed at the sidewalls of the dummy gate structure, as described in paragraph [0070].)
Claims 32 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Frougier as modified by Pan as applied to claim 28 above, and further in view of Glass.
Regarding claim 32, Frougier as modified by Pan discloses the method of Claim 28, further comprising forming an etch stop layer over the epitaxial source/drain structure (Figure 10 illustrates the protective layer 1010, described in paragraphs [0081] and [0086], deposited on the nanosheet channels comprising the source/drain structure).
Frougier as modified by Pan lacks the etch stop layer being formed over a remaining portion of the first dielectric layer (310/320).
However, Glass discloses a similar device, in which the first dielectric layer as disclosed in Frougier as modified by Pan also comprises a relaxed buffer layer part composed of the same material. In Glass, figure 2, the first dielectric layer comprises dielectric relaxed buffer layer 126 [0025], which remains after other portions of the first dielectric layer are removed. Thus, the etch stop layer (layer 174, a contact barrier layer, which can function as an etch stop) is deposited over the remaining portion of the first dielectric layer.
Therefore, it would have been obvious to a person of ordinary skill in the art before the time of filing to configure the first dielectric layer of Frougier as modified by Pan as in Glass to incorporate a relaxed buffer layer in order to improve structural quality (Moutanabbir et al. - non patent literature, Monolithic infrared silicon photonics: The rise of (Si)GeSn semiconductors. ).
Regarding claim 33, Frougier in view of Pan as modified by Glass discloses the method of Claim 32, wherein the etch stop layer is coupled to the first dielectric layer. The first dielectric layer of Frougier in view of Pan as modified by Glass, as discussed in the rejection of claim 32, is also coupled to the etch stop layer physically, as it is in physical contact with that layer. See Glass figure 2, where the remaining part of first dielectric layer (126) is physically connected to the etch stop layer (174).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATRINA M H WALJESKI-MOSES whose telephone number is (571)272-0731. The examiner can normally be reached Mon- Fri 7:30 am- 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KATRINA WALJESKI-MOSES/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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