Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 5-6, 8-9 and 14 is rejected under 35 U.S.C. 103 as obvious over Fish et al. (Pub. No.: US 2006/0132051 A1).
Regarding Claim 1, Fish et al. discloses a display device comprising: a substrate including a light emitting area and a non-light emitting area adjacent to the light emitting area (Par. 0031-0035; Figs. 4-5 - substrate 120); a first conductive layer disposed on the substrate in the light emitting area and the non-light emitting area (Par. 0031-0035; Figs. 4-5 – first conductive layer comprising first capacitor plate 132 (in the light emitting area) and gate 122 (in the non-light emitting area));
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a second conductive layer disposed on the first conductive layer and disposed in the light emitting area (Par. 0031-0035; Figs. 4-5 – second conductive layer 27); a first insulating film disposed between the first conductive layer and the second conductive layer, wherein the first insulating film is disposed in the light emitting area, overlaps the first conductive layer and the second conductive layer in the light emitting area, and has a first permittivity (Par. 0031-0035; Fig. 4 – first insulating film 130 (first insulating layer) having a first dielectric permittivity); and a second insulating film disposed on the first insulating film and between the first insulating film and the second conductive layer, disposed in the light emitting area and the non-light emitting area, overlapping the first insulating film and having a second permittivity greater than the first permittivity (Par. 0031-0035; Fig. 4 – second insulating film 140 (first insulating layer) having a second dielectric permittivity; this prior art clearly teaches that the permittivity of the second insulating film, at least according to one embodiment, may be greater than the permittivity of the first insulating film). Fish et al. does not disclose the first insulating film is disposed only in the light emitting area. Fish et al. explains ways to increase the capacitance of capacitors 32 and 34 (Figs. 2-3). To achieve this, the capacitors are stacked vertically instead of being placed horizontally side-by-side. This allows one to increase the area of the capacitors, thereby achieving higher capacitance. This prior art also teaches that the values of the two capacitors can be independently adjusted by varying the thicknesses and the materials of the first insulating film and the second insulating film. However, if the same first insulating film is applied over both the light emitting area and the non-light emitting area, it will limit the performance of the switchable device (12) placed in the non-light emitting area. This is because. the thickness and the material of the gate insulating film cannot be optimized independently. To overcome this constraint, one could easily put separate dielectric materials for the capacitor and the switchable device.
Fish et al. discloses the claimed invention except for the display device, wherein the first insulating film is disposed only in the light emitting area. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the display device, wherein the first insulating film is disposed only in the light emitting area, since it has been held that the provision of adjustability, where needed, involves only routine skill in the art. In re Stevens, 1010 USPQ 284 (CCPA 1954).
Regarding Claim 2, Fish et al., as applied to claim 1, discloses the display device, wherein the first insulating film and the second insulating film include different materials (Par. 0034; Fig. 4).
Regarding Claim 5, Fish et al., as applied to claim 1, discloses the display device, wherein the first insulating film has a same shape as the first conductive layer in the light emitting area (Fig. 4).
Regarding Claim 6, Fish et al., as applied to claim 1, discloses the display device, wherein, the first conductive layer defines at least one first opening disposed in the light emitting area, and the first insulating film defines at least one second opening disposed in the light emitting area (Fig. 4).
Regarding Claim 8, Fish et al., as applied to claim 1, discloses the display device, further comprising: a light emitting diode disposed on the first conductive layer and disposed in the light emitting area (Fig. 4).
Regarding Claim 9, Fish et al., as applied to claim 8, discloses the display device, wherein the light emitting diode includes: the second conductive layer; a light emitting layer disposed on the second conductive layer; and a common electrode disposed on the light emitting layer (Par. 0031-0035; Fig. 4 – second conductive layer 27; light emitting layer 2; common electrode 28).
Regarding Claim 14, Fish et al., as applied to claim 1, discloses the display device, wherein each of the first conductive layer and the second conductive layer includes a metal material (Par. 0031).
Claim 3 is rejected under 35 U.S.C. 103 as obvious over Fish et al. (Pub. No.: US 2006/0132051 A1), as applied to claim 1, further in view of Myung et al. (Pub. No. : KR 20210045581A).
Regarding Claim 3, Fish et al., as applied to claim 1, does not explicitly disclose the display device, wherein the first insulating film includes at least one selected from a group consisting of acrylate and siloxane hybrid.
However, Myung et al. teaches the display device, wherein the first insulating film includes at least one selected from a group consisting of acrylate and siloxane hybrid (abstract; Par. 0056 - this prior art teaches use of a low dielectric constant material comprising acrylate and siloxane in display devices as it improves the performance of the device). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Myung et al. to adapt the display device, wherein the first insulating film of Fish et al. includes at least one selected from a group consisting of acrylate and siloxane hybrid in order to suppress parasitic capacitance and hence improve device performance.
Claims 4 & 10-12 are rejected under 35 U.S.C. 103 as obvious over Fish et al. (Pub. No.: US 2006/0132051 A1), as applied to claims 1 & 8, further in view of Lee (Pub. No. : US 2021/0020714 A1).
Regarding Claim 4, Fish et al., as applied to claim 1, does not explicitly disclose the display device, wherein the second insulating film includes a photo-sensitive polyimide-based resin.
However, Lee, at least implicitly, teaches the display device, wherein the second insulating film includes a photo-sensitive polyimide-based resin (Par. 0089; Fig. 7 - second insulating film P_IS2 includes photo-sensitive polyimide). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Lee to adapt the display device, wherein the second insulating film of Fish et al. includes a photo-sensitive polyimide-based resin in order to have an insulating material that provides good isolation with reasonable dielectric constant and can be formed and patterned with simple processes. .
Regarding Claim 10, Fish et al., as applied to claim 8, discloses the display device, further comprising: a transistor disposed on the substrate and disposed under the first conductive layer (Par. 0031-0035; Fig. 4 – drive transistor 12). Fish et al. does not disclose the display device, further comprising: the transistor disposed under the first conductive layer. However, Lee, at least implicitly, teaches the display device, further comprising: the transistor disposed under the first conductive layer (Fig. 7). Fish et al. teaches a bottom-gate transistor. If it were a top gate transistor, at least a portion of the transistor would be disposed under the first conductive layer. Top-gate transistors are ubiquitously known and are known to provide better device performances. Lee teaches such a top-gate transistor, the teachings of which could be incorporated to modify the device of Fish et al. to achieve better device performance.
It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Lee to adapt the display device, further comprising: the transistor disposed under the first conductive layer of Fish et al. in order to have an better device performance.
Regarding Claim 11, modified Fish et al., as applied to claim 10, discloses the display device, wherein the transistor includes: an active layer disposed on the substrate; a gate electrode disposed on the active layer; and a source electrode and a drain electrode connected to the active layer on the gate electrode (Lee – Par. 0084; Fig. 7 - active layer SM; substrate SUB; gate electrode GE; source electrode SE; drain electrode DE).
Regarding Claim 12, modified Fish et al., as applied to claim 10, discloses the display device, wherein the transistor is electrically connected to the light emitting diode through the first conductive layer (Lee – Par. 0084; Fig. 7 in light of rejection of claim 10).
Claim 13 is rejected under 35 U.S.C. 103 as obvious over Fish et al. (Pub. No.: US 2006/0132051 A1), as applied to claim 1.
Regarding Claim 13, Fish et al., as applied to claim 1, does not explicitly disclose the display device, wherein the first conductive layer further includes a data line. Fish et al. teaches first conductive layer comprises a gate electrode. It is silent regarding whether the data line is formed of the first conductive layer. The Examiner takes OFFICIAL NOTICE that the display device, wherein the first conductive layer further includes a data line is well known in the art (see, for example, US 20110109532 A1 – Par. 0015 & 0024). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings well-known in the industry to adapt the display device, wherein the first conductive layer of Fish et al. further includes a data line in order to satisfy overall design of the device.
Claim 15 is rejected under 35 U.S.C. 103 as obvious over Fish et al. (Pub. No.: US 2006/0132051 A1), as applied to claim 14, further in view of Min (Pub. No. : US 2015/0069340 A1).
Regarding Claim 15, Fish et al., as applied to claim 14, does not explicitly disclose the display device, wherein the second conductive layer includes at least one selected from a group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). However, Min, at least implicitly, teaches the display device, wherein the second conductive layer includes at least one selected from a group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO) (Par. 0037; Fig. 2 - the second conductive layer comprising pixel electrode 710 is formed of transparent conductor such as ITO or IZO). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Min to adapt the display device, wherein the second conductive layer of Fish et al. includes at least one selected from a group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO) in order to fabricate a display device with a certain overall design.
Response to Arguments
Applicants’ arguments filed on 05/12/2026 have been fully considered but they are moot because of the new grounds of rejection necessitated by amendments made to the claims.
Allowable Subject Matter
Claim 7 is allowed. The following is an examiner's statement of reasons for allowance:
Regarding Claim 7: The prior art of record to the examiner’s knowledge does not teach or render obvious the instant invention, particularly characterized by a display device comprising: a light emitting area and a non-light emitting area adjacent to the light emitting area; a first conductive layer disposed on a substrate in the light emitting area and the non-light emitting area; a second conductive layer disposed on the first conductive layer and disposed in the light emitting area; a first insulating film disposed on the first conductive layer, overlapping the first conductive layer and the second conductive layer in the light emitting area, and having a first permittivity; and a second insulating film disposed between the first insulating film and the second conductive layer, disposed in the light emitting area and the non-light emitting area, overlapping the first insulating film and the first conductive layer, and having a second permittivity greater than the first permittivity, wherein the first conductive layer defines at least one first opening disposed in the light emitting area, the first insulating film defines at least one second opening disposed in the light emitting area, and wherein-the first opening and the second opening overlap each other.
The most relevant prior art reference due to Fish et al. (Pub. No.: US 2006/0132051 A1) substantially discloses a display device comprising: a light emitting area and a non-light emitting area adjacent to the light emitting area (Par. 0031-0035; Fig. 4); a first conductive layer disposed on a substrate in the light emitting area and the non-light emitting area (Par. 0031-0035; Fig. 4 – first conductive layer 132 (first capacitor plate); substrate 120);
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a second conductive layer disposed on the first conductive layer and disposed in the light emitting area (Par. 0031-0035; Fig. 4 – second conductive layer 27); a first insulating film disposed on the first conductive layer, overlapping the first conductive layer and the second conductive layer in the light emitting area, and having a first permittivity (Par. 0031-0035; Fig. 4 – first insulating film 130 (first insulating layer) having a first dielectric permittivity); and a second insulating film disposed between the first insulating film and the second conductive layer, disposed in the light emitting area and the non-light emitting area, overlapping the first insulating film and the first conductive layer, and having a second permittivity greater than the first permittivity (Par. 0031-0035; Fig. 4 – second insulating film 140 (first insulating layer) having a second dielectric permittivity; this prior art clearly teaches that the permittivity of the second insulating film, at least according to one embodiment, may be greater than the permittivity of the first insulating film).
Additionally, the prior arts made of record and not relied upon are considered pertinent to applicant's disclosure. See form PTO-892.
However, none of these prior art references indicated above or the prior arts made of record in form PTO-892, disclose all the limitations of claim 7 (the individual limitations may be found in a plurality of prior arts but there is no motivation to combine). Because no reference alone teaches all the limitations, nor is there any motivation to combine the prior arts to construct all the limitations of this independent claim, claim 7 is deemed patentable over the prior arts.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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05/28/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893