Prosecution Insights
Last updated: May 29, 2026
Application No. 18/455,857

PHOTONIC PACKAGES WITH MODULES AND FORMATION METHOD THEREOF

Non-Final OA §103
Filed
Aug 25, 2023
Priority
May 17, 2023 — provisional 63/502,684
Examiner
BAIG, ANEESA RIAZ
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
32 granted / 34 resolved
+26.1% vs TC avg
Moderate +7% lift
Without
With
+7.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
19 currently pending
Career history
56
Total Applications
across all art units

Statute-Specific Performance

§103
77.8%
+37.8% vs TC avg
§102
15.6%
-24.4% vs TC avg
§112
5.6%
-34.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 34 resolved cases

Office Action

§103
Attorney’s Docket Number: TSMP20230005US02 Filing Date: 08/25/2023 Claimed Priority Date: 05/17/2023 (PRO 63/502684) Applicant: Chen Examiner: Aneesa Baig DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The application serial no. 18/455857 filed on 08/25/2023 has been entered. Pending in this Office Action are claims 1-20. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 2,4,10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Budd et. al (US 20170186670 A1, Hereinafter Budd) in view of Chang et al (US 20150108659 A1, Hereinafter Chang). Regarding claim 1, Budd(e.g., Fig 1, 2A-2C-7[0020]-[0050]) shows most aspects of the invention including, A method comprising: bonding a first module (e.g., interposer 130) over a package component (application board 150), wherein the first module comprises: a substrate (substrate 132); and through-vias penetrating through the substrate (134); bonding an electronic die on the first module (Chip 120); and bonding a photonic die over the electronic die (optoelectronic device 140) While the method of Budd shows forming a photonic package, it does not show the first module (130) encapsulated in a molding compound. Chang (e.g., Fig 1G, 2A-2E [0030]-[0040]), on the other hand and in a related field of 3D packaging, teaches a interposer and several devices disposed thereon in a molding compound (22). Chang teaches this molding compound placed around and in between the dies 11 and 300 and planarizing the molding compound to revel active surfaces, as in this case, vias 118 ([0030]) . Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have molding around a first module of Budd, as taught by Chang, as molding is commonly used in 3D stacking and conventionally is used to contain and protect devices therein and molding a device is a known method for its conventional purpose would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007). Regarding Claim 2, See comments from Claim 1 above, as they would be considered repeated here. Regarding Claim 4, Budd shows the material of the substrate in the first module (132 [0033]) is a dielectric material (glass). Regarding Claim 10, Budd shows there are no active or passive devices in the first module, interposer (130). Regarding Claim 11, Budd shows there are no horizontal conductive lines within the first module, interposer (130). Regarding Claim 12, Budd shows a structure comprising: a package substrate (e.g., 150); a first module (130) over and electrically coupling to the package substrate, wherein the first module comprises: a substrate (132); and through-vias penetrating through the substrate (134); an electronic die over and bonding to the first module (chip 120), wherein the electronic die is electrically coupled to the package substrate through the first module ; and a photonic die over and signally coupling to the electronic die (e.g., 140). While the structure of Budd shows forming a photonic package, it does not show the first module (130) encapsulated in a molding compound. Chang (e.g., Fig 1G, 2A-2E [0030]-[0040]), on the other hand and in a related field of 3D packaging, teaches a interposer and several devices disposed thereon in a molding compound (22). Chang teaches this molding compound placed around and in between the dies 11 and 300 and planarizing the molding compound to revel active surfaces, as in this case, vias 118 ([0030]) . Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have molding around a first module of Budd, as taught by Chang, as molding is commonly used in 3D stacking and conventionally is used to contain and protect devices therein and molding a device is a known method for its conventional purpose would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007). Regarding Claim 13, Budd shows the top and bottom of the vias (134) are coplanar with the top and bottom surfaces of the first module (interposer 130) Regarding Claim 14, Budd shows there are no horizontal conductive lines within the first module, interposer (130). Allowable Subject Matter Claims 3,5-9,15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 18-20 are allowable. The following is an examiner’s statement of reasons for allowance: Regarding Claim 18, the closest identified prior art, Budd in view of Chang discloses a structure at per claim 12, but it does not disclose or make obvious the following : a second plurality of solder regions overlying and contacting top surfaces of the plurality of metal posts; an electronic die over and bonding to the second plurality of solder regions; Rather, Budd shows the electronic die bonded to the interposer by hybrid bonding. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANEESA RIAZ BAIG whose telephone number is (571)272-0249. The examiner can normally be reached Monday-Friday 8am-5pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANEESA RIAZ BAIG/Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
Read full office action

Prosecution Timeline

Aug 25, 2023
Application Filed
Sep 16, 2025
Response after Non-Final Action
Jan 20, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12622305
A SEMICONDUCTOR STRUCTURE AND METHOD MAKING THE SAME
2y 8m to grant Granted May 05, 2026
Patent 12616012
STACKED RANDOM-ACCESS MEMORY DEVICES
4y 8m to grant Granted Apr 28, 2026
Patent 12616043
PACKAGE COMPRISING INTEGRATED DEVICES
3y 9m to grant Granted Apr 28, 2026
Patent 12615820
SEMICONDUCTOR DEVICE
2y 9m to grant Granted Apr 28, 2026
Patent 12610874
CONNECTION STRUCTURAL BODY AND SEMICONDUCTOR DEVICE
3y 1m to grant Granted Apr 21, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
99%
With Interview (+7.4%)
3y 4m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 34 resolved cases by this examiner. Grant probability derived from career allowance rate.

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