DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election, with traverse, of species D.I II , claims 1-4 and 8 -11 in the ”Response to Election / Restriction Filed - 02/27/2026 ”, is acknowledged. The applicant further indicated claims 5-7 and 12-15 are provisionally withdrawn . Based on the option, given in in th e restriction requirement, that “the Office Action is only guideline s , and not a binding to the applicant to elect from. However, as detailed below later, Applicant must include an identification of the species that is elected, and a listing of all claims readable thereon, including any claims subsequently added ” the traversal argument has been given full consideration but are not persuasive for claims 12-15, which are distinct then others claims and embodiments. T he requirement is still deemed proper , and is therefore made FINAL, and thus the required provisional election (see MPEP § 818.03(b) ) becomes an election without traverse. In view of the above, this office action considers claims 1-1 5 pending for prosecution , of which, non-elected claims 1 2 - 15 are withdrawn, and elected claims 1-1 1 are examined on their merits. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention . . Notes : when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as ( 10 ; Fig 6 ; [00 44 ]) = (element 10 ; Figure No. 6 ; Paragraph No. [00 44 ]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The primary reference citation may not be preceded by the inventor tag, wherein the other reference citation will carry inventor tag. These conventions are used throughout this document. Claims 1 - 7 and 10 -11 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Ahmed; Sayeed et al. (US 20060274561 A1) hereinafter Ahmed . Rega r ding claim 1. Ahmed teaches a semiconductor power module ( 10 ; Fig 6; [0044]; first cited in Figs 1,2A,2B, 3-5; [0024]) for a power converter 70 ; Figs 7-10 for supplying current to an electrical axle drive (l oad 64 ) in an electric vehicle ([0006] AC load such as a three-phase AC motor in an electric or hybrid vehicle ) and/or a hybrid vehicle, comprising ( see the entire document, Fig s 2B, 4 , 6A,9 along with the subject matters of relevant other figures 1, 2A, 3, 5,7,10 , specifically, as cited below ) ; Ahmed Fig 6 and Fig 9 a plurality of semiconductor switching elements ( comprising { transistor 48, diode 50} ; Fig 2B; [00 41 ] ) configured to generate an output current on a basis of an input current provided by a voltage source by switching the semiconductor switching elements ( 48,50 ) , wherein the semiconductor switching elements comprise at least one diode ( 50 ) which each have an anode ( anode ; [0031] ) and a cathode ( cathode ; [0030] ) ; Ahmed Fig 2B and Fig 4 a first leadframe ( 1 6 /116 ; Fig 2b ,9 ; labelled as lead and plate 44a ) and a second leadframe ( 1 8 /118 ) having a plurality of conductor tracks ( 28a-28b ; 30a-30b. 32a, 32b; Fig 2B; [00 42 ] ) configured to electrically connect the semiconductor switching elements ( 48,50 ) in order to form a half-bridge ([0039]) having a high side ( 20a ; Fig 2B; [0024]) and a low side ( 20 b ) on a basis of the semiconductor switching elements ( 48,50 ) , wherein the first leadframe and the second leadframe are provided by regions of an upper metal layer ( 44a/44b ; Figs 2B, 4 ) of a multilayered substrate ( 40 comprising { 40a,40b,40c }; Fig 4 ; [0028 , 0032 ]) which are electrically insulated from one another (by 40b ) or potentially isolated ( inherent because of insulating layer 40b ), wherein electrical contact is made with the diodes ( 50s depicted at left and right connected though 45; Fig 2B, 4 ) between the first leadframe and the second leadframe in such a way that the anode of the diode ( 50) faces a cooler ( 42 ; [0027]) which is mechanically connected and thermally coupled to the semiconductor power module ( 10 ), wherein the cooler ( 42 ) is connected to the multilayered substrate ( 40 ) from below ( depicted in fig 4 ). Regarding claim 2. Ahmed as applied to t he semiconductor power module according to claim 1, further teaches, wherein the first leadframe ( 118/18; Fig 9; labelled as lead and plate ) is assigned to the high side ( 2a; Fig 2B ) and the second leadframe ( 116/16; Fig 9; labelled as lead and plate ) is assigned to the low side. Regarding claim 3. Ahmed as applied to the semiconductor power module according to claim 1, further teaches, wherein the first leadframe ( 1 6 /1 16 ; Fig s 2b, 9; labelled as lead and plate ) and the second leadframe ( 18 /118 ; Fig s 2B, 9; labelled as lead and plate ) are provided by regions of an upper metal layer ( 44a/44b ; Figs 2B, 4 ) of a multilayered substrate ( 40 comprising { 40a,40b,40c }; Fig 4 ; [0028 , 0032 ]) which are electrically insulated from one another (by 40b ) and potentially isolated ( inherent because of insulating layer 40b ) , and wherein the cooler the cooler ( 42 ) is connected to the multilayered substrate ( 40 ) from below ( depicted in fig 4 ). Regarding claim 4. Ahmed as applied to the semiconductor power module according to claim 1, further teaches, wherein the first leadframe ( 16/116; Fig 2b,9; labelled as lead and plate 44a ) is a positive-pole DC leadframe , wherein the second leadframe (18/118) is an AC leadframe ([0042]) , wherein the cooler ( 42 ) is arranged on a side of the semiconductor power module ( 10 ) which faces the second leadframe , wherein the anode of the diode is arranged so as to face the second leadframe and/or at least one further diode is arranged with its anode facing a third leadframe (( 16/116 for 20b ; Fig 2B,9; labelled as lead and plate 44b ) , which is a negative-pole DC leadframe . Regarding claim 5 . Ahmed as applied to the semiconductor power module according to claim 1, further teaches, wherein the semiconductor switching elements ({48,50}) also comprise a plurality of transistors (48; depicted at least 12 in Fig 2B ) which each have a positive-pole current electrode ( P/72 Fig 7; [0046] The collector 72 of a first transistor Q1 is coupled to a positive DC supply line ) and a negative-pole current electrode ( N/104; Fig 7; [0048] ) . Regarding claim 6 . Ahmed as applied to the semiconductor power module according to claim 5 , further teaches, wherein the plurality of transistors (48) comprise insulated-gate bipolar transistors (48, IGBT; [0030]) . Regarding claim 7 . Ahmed as applied to the semiconductor power module according to claim 5 , further teaches, wherein the negative-pole current electrode (N) is arranged so as to face away from the second leadframe (18/118) . Regarding claim 10. Ahmed as applied to the semiconductor power module according to claim 1, further teaches, wherein (Fig 4) the first and/or second leadframes (16/18) are provided by an upper metal layer (40c//(44a/44b) of a multilayered substrate ( 20 ) , which additionally comprises a lower metal layer (40a) and a layer of insulation (40b) arranged between the upper metal layer (40c) and the lower metal layer (40b) . Regarding claim 11. Ahmed as applied to the semiconductor power module according to claim 4, further teaches, wherein (Figs ¾; [0027]) the first (16 in 20a) , second (18) and/or third leadframes (16 itn 20b) are provided by an upper (40c) metal layer (copper) of a multilayered substrate (20) , which additionally comprises a lower metal layer (40a, copper) and a layer of insulation (40n) arranged between the upper metal layer and the lower metal layer. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made invention. Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Ahmed; Sayeed et al. (US 20060274561 A1) hereinafter Ahmed . in view of HAYASHIGUCHI; Masashi et al. (US 20240006402 A1) hereinafter Hayashiguchi Regarding claim s 8 , 9 . Ahmed as applied to the semiconductor power module according to claim 1, is silent on , wherein the semiconductor switching elements ( comprising { transistor 48, diode 50} ; Fig 2B; [0041]) , For claim 8: are based at least partially on a gallium oxide compound. For claim 9; wherein the diodes (diodes 50) are based at least partially on the gallium oxide compound. .However, in the analogous art , Hayashiguchi t eaches a power module (semiconductor device) with switching elements, which are either MOSFETs or IGBTs to be used in an inverter, for example, and performs power conversion through switching operations by the switching elements ([0002]); wherein (Figs 1-6; [0034]) The switching circuit 1 includes a MOSFET 11 as a first MOSFET, an IGBT 12 as a first IGBT, and a Schottky barrier diode (hereinafter “SBD”) 13 as a first Schottky barrier diode ; all of those comprise , a t least. semiconductor material, inter alia, Ga.sub.2O.sub.3 ( gallium oxide) compound. T herefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention, to select Hayashiguchi’s material for Ahmed ’s transistor 48, diode 50 , and thereby the combination of ( Ahmed and Hayashiguchi ) ’ switching elements and diodes comprise gallium oxide compound as claimed, since, since on the basis of its suitability for the intended use as a matter of obvious design choice In re Leshin , 227 F.2d 197, 125 USPQ 416 (CCPA 1960), see MPEP § 2144.07. T he selection of a known material as a ingredients of (additive) of the claimed material is a matter of choice which a person of ordinary skill in the art would have found obvious, In re Dailey , 357 F.2d 669, 149 USPQ 47 (CCPA 1966) see MPEP § 2144. 04.IV (B). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form PTO-892. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT MOAZZAM HOSSAIN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-7960 . The examiner can normally be reached on FILLIN "Work schedule?" \* MERGEFORMAT M-F: 8:30AM - 6:00 PM . EST. Examiner interviews are available via telephone, in-person, and video The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form PTO-892. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT MOAZZAM HOSSAIN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-7960 . The examiner can normally be reached on FILLIN "Work schedule?" \* MERGEFORMAT M-F: 8:30AM - 6:00 PM . EST. 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For more information about the PAIR system, see http://pair-direct.uspto.gov. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov . Visit https://www.uspto.gov/patents/apply/patent- center for more information about Patent Center, and https://www.uspto.gov/patents/docx for information about filing in DOCX format. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOAZZAM HOSSAIN/ Primary Examiner, Art Unit 2898 March 2 6, 2026