DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/11/2024 and 04/16/2025 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to because Fig. 14A upper gate of PDA should be 134U1 and lower gate of PUA should be 134L1 (as shown in Fig. 14C and Fig. 14D). The gate column where 134U2 and 134L2 should be annotated 134U1 and 134U2. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 15-16, 18, 20- 22, 24 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Xie (US 20230086033 A1)
Regarding claim 15, Xie discloses a method comprising:
forming nanostructures (110, 112, Fig. 2D) above a semiconductor fin (101, Fig. 2D); the semiconductor fin extending from an isolation region (104, Fig. 2D);
forming a lower gate structure (lower 126, Fig.9A), an upper gate structure (upper 126, Fig. 8A) and a gate isolation region (128, Fig. 9D), the lower gate structure wrapped around a lower subset of the nanostructures (Fig. 9A), the upper gate structure wrapped around an upper subset of the nanostructures (Fig.9A)
the gate isolation region adjacent the lower gate structure and the upper gate structure (Fig. 9D);
removing a portion of the isolation region (105 formed in 104, Fig, 12D);
depositing a dielectric layer (106, 136, Fig. 12D) on a back-side of the isolation region; and
forming a cross-coupling contact (1101, Fig. 11D, or 136, 138, Fig. 12D) having a line portion (portion of 138 on top of 104) extending along a surface of the dielectric layer and having a gate via portion (portion of 138 penetrating 104) extending through the dielectric layer (136) and the isolation region (104) to contact the lower gate structure (lower 126, Fig. 12D), the line portion crossing beneath the gate isolation region (128).
Regarding claim 16, Xie discloses the method of claim 15, further comprising:
growing a lower source/drain region (¶ [0054], lower portion of 122, Fig. 6A), in a recess (recess in Fig. 5A) in the semiconductor fin, the lower gate structure formed adjacent the lower source/drain region; and
growing an upper source/drain region (upper portion of 122, Fig. 6A) in the recess and over the lower source/drain region, the upper gate structure formed adjacent the upper source/drain region.
Regarding claim 18, Xie discloses the method of claim 15, wherein the lower gate structure comprises a gate dielectric (¶ [0031] disclosing the gate includes a gate dielectric over the channel and a gate conductor over the gate dielectric) and a gate electrode (126, Fig. 8A), the gate via portion (portion of 138 penetrating 104, Fig. 12D) extending through the gate dielectric (104) to contact the gate electrode (126, Fig. 12D).
Regarding claim 20, Xie discloses the method of claim 15, wherein the cross-coupling contact is I-shaped in a top-down view (1101, Fig, 11E).
Regarding claim 21, Xie discloses a method comprising:
forming a trench isolation region (124, Fig. 8A) between a plurality of first nanostructures (first 112, Fig. 8A) and a plurality of second nanostructures (second 112, Fig. 8A);
forming a first gate structure (lower left 126, Fig. 8D) and a second gate structure (lower right 126, Fig. 8D) the first gate structure formed around the first nanostructures (first 101, Fig. 8D), the second gate structure formed around the second nanostructures (second 101, Fig. 8D);
forming a gate isolation region (128, Fig. 8D) between the first gate structure (first 126, Fig. 8D) and the second gate structure (second 126, Fig, 8D), the gate isolation region formed on a front-side (on first surface of 104, Fig. 8D) of the trench isolation region;
depositing a dielectric layer (¶ [0040] disclosing forming 106 in 104 on second surface of 104) on a back-side of the trench isolation region; and
forming a cross-coupling contact (1101, Fig. 11D, or 136,138, Fig. 12D) having a line portion (portion of 138 on top of 104) extending along a surface of the dielectric layer and having a gate via portion (portion of 138 penetrating 104) extending through the dielectric layer (136) and the trench isolation region (124) to contact the lower gate structure (lower 126, Fig. 12D), the line portion crossing beneath the gate isolation region (128) and the second gate structure.
Regarding claim 22, Xie discloses the method of claim 21, further comprising:
forming a source/drain contact (130, Fig. 9A) adjacent to the second gate structure, the cross-coupling contact (BPR 105, Fig. 9B) further having a source/drain via portion (portion connecting 105 and 130, Fig. 9B) extending through the dielectric layer to contact the source/drain contact.
Regarding claim 24, Xie discloses the method of claim 21, further comprising:
forming a source/drain contact (contact 130) adjacent to the second gate structure;
forming a source/drain via (via extending from 105 to 130, Fig. 9B) extending through the dielectric layer to contact the source/drain contact; and
forming a conductive line (105) coupling the source/drain via to the cross-coupling contact (1101, Fig. 11D, through daisy-chained coupling via common conductive element 105).
Regarding claim 25, Xie discloses the method of claim 24, wherein the line portion of the cross-coupling contact (1101, Fig. 11D) has a single segment (1101) extending in a direction parallel to a longitudinal axis of the first gate structure (1101, Fig. 11E).
Regarding claim 26, Xie discloses (Fig. 8D) discloses the method of claim 21, further comprising: forming a third gate structure (upper left 126, Fig. 8D) above and coupled to the first gate structure; and forming a fourth gate structure (upper right 126) above and coupled to the second gate structure.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19, 27, 28 are rejected under 35 U.S.C. 103 as being unpatentable over Xie (US 20230086033 A1) in view of Xie2 (US 20230345691 A1)
Regarding claim 19, Xie discloses the method of claim 15 but is silent to the shape of the cross-coupling contact being L-shaped.
Xie2 discloses the analogous art of an SRAM device comprising a cross- coupling contact being L-shaped (Fig. 4B). One of ordinary skill in the art would have selected the shape of the cross-coupling contact to be L-shaped or I-shaped for optimal solutions and the selection would not yield unpredictable results. Therefore, one of ordinary skill in the art before the filing date of the invention would have selected the L-shaped contact structure of Xie for the contact shape of Xie as a result of routine experimentations.
Regarding claim 27-28, Xie discloses the method of claim 26 but is silent to the pull-up transistor, the pull-down transistor, and the pass-gate transistor.
Xie2, discloses an analogous SRAM with the two pull-up (PU) transistors upper gate structures (third and fourth gate structures) and two pull-down (PD) transistors and two pass-gate (PG) transistors on the lower gate structures (first and second) (Figs. 1A-1B, PU transistors 310, 320; PD transistors 410, 420; PG transistors 210, 220; the gate portion with the bracket is for used transistors, the gate portion without the bracket is for unused transistors).
Xie discloses the method of coupling a common source/drain to a common gate using nanowires fin and upper lower gate structure; though not explicitly named the method for forming the SRAM device, one of ordinary skill in the art would have appreciated the fundamental elements could be applied to form a 6T SRAM device. Such, one of ordinary skill in the art before the filing date of the invention would have applied the method of Xie to form a 6T SRAM yielding predictable results.
Allowable Subject Matter
Claims 29-34 are allowed.
Claims 17, 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 17 would be allowable for disclosing forming a word line extending through the dielectric layer and the gate isolation region and connecting with a back-side interconnect structure via a contact. The back-side interconnect structure is formed under the dielectric layer. The prior art (Xie) does not teach a word line. The secondary art (Xie2) does not teach a word line interconnect structure below the dielectric layer. Any attempt to combine this feature would require a word line interconnect structure formed below a dielectric layer and providing a via contact through the dielectric layer and the gate insulation to make connection with the intended transistor.
Claim 23 would be allowable for disclosing the cross-coupling contact of claim 22 further having the first segment and the second segment perpendicular to each other and the first segment underneath the second gate structure crossing beneath the gate isolation and parallel to the first gate structure making it extending below and aligned along with the second gate structure (first and second gate structure are parallel). The prior art does not disclose the cross-coupling contact to have the two segments perpendicular to each other. Xie2 (below) discloses the cross-coupling contact with two segments perpendicular with each other, but the first segment contacting the common gate does not align with the second gate structure.
Claim 29 would be allowable for disclosing the allowable subject matter in claim 23. Claim 30-34 are allowable for depending on allowable claim 29.
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The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chiu (US 20220122993 A1) discloses the SRAM device structure with a short cross-coupling contact due to a particular shape of the gate isolation structure, and Do (US 20180175024 A1) discloses different cross-coupling contact arrangement for the device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T HOANG whose telephone number is (571)272-5622. The examiner can normally be reached M-F 8:00 - 5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DTH/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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