Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to a restriction requirement mailed on 11/12/2025, the Applicant elected Invention I (Group I) drawn to a method encompassing claims 1-16, without traverse on 11/12/2025. The Applicant canceled claims 17-20 directed to a non-elected Invention II (Group II). The Applicant added new method claims 21-24 directed to the elected Invention I (Group I).
Elected claims 1-16 and 21-24 are examined below.
Information Disclosure Statement (IDS)
Two information disclosure statements submitted on 08/25/2023 (“08-25-23 IDS”) and the 11/19/2024 (“11-19-24 IDS”) are in compliance with the provisions of 37 CFR 1.97. Accordingly, the 08-25-23 IDS and 11-19-24 IDS are being considered by the examiner.
Specification
The specification is objected to, because the title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: ELECTRICAL TESTING OF SEMICONDUCTOR PACKAGES THAT INCLUDE BUILD-UP STRUCTURE AND CORE STRUCTURE TO BE BONDED
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2021/0343547 A1 to Chang et al. ("Chang").
Figs. of Chang have been provided to support the rejections below:
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Regarding independent claim 1, Chang teaches a method, comprising:
forming a build-up structure 128 (para [0020] - “Interconnect structure 128 is formed over semiconductor substrate 124. In accordance with some embodiments, interconnect structure 128 includes an Inter-Layer Dielectric (ILD) 128a over semiconductor substrate 124 and filling the space between the gate stacks of transistors (not shown) in integrated circuit devices 126.”) that includes a plurality of metal layers 128c (para [0022] - “metal lines 128c”) embedded a plurality of dielectric layers 128a, IMDs (para [0020] - “…interconnect structure 128 includes an Inter-Layer Dielectric (ILD) 128a…”; para [0022] - “Interconnect structure 128 may further include a plurality of dielectric layers over the ILD and the contact plugs. Metal lines 128c and vias 128d are formed in the dielectric layers (also referred to as Inter-Metal Dielectrics (IMDs)).”);
forming a core structure 150 (para [0047] - “Integrated circuit dies 150”) that embeds a passive device 154 (para [0044] - “The devices 154 may be…capacitors, resistors, etc.”; see Fig. 8);
performing a first electrical test on the build-up structure 128 (Further referring to FIG. 1, device dies 122 are probed, for example, by putting the pins of the probe card 141 into contact with solder regions 134…”);
performing a second electrical test on the core structure 150 (para [0047] - “Integrated circuit dies 150 are probed, for example, using probe card 141′, so that defective integrated circuit dies 150 are found, and known-good-dies (KGDs) are determined. The probing is performed on each of integrated circuit dies 150.”); and
after performing the first electrical test (see Fig. 1) and the second electrical test (see Fig. 8), bonding the build-up structure 128 to the core structure 150 (para [0052] - “In FIG. 9, the integrated circuit dies 150 which are KGDs are bonded to the KGDs 122 attached to the carrier substrate 148. The respective process is illustrated as process 820 in the process flow 800 as shown in FIG. 23.”).
Regarding claim 5, Chang teaches the core structure 150 that comprises polyimide 168 (para [0049] - “The dielectric layer 168 may be a polymer such as PBO, polyimide, BCB, or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; the like, or a combination thereof.”).
Regarding claim 6, Chang teaches the passive device that comprises a metal-insulator-metal (MIM) capacitor (capacitor is at least formed by parallel metal plates sandwiching an insulator).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
(1). Determining the scope and contents of the prior art.
(2). Ascertaining the differences between the prior art and the claims at issue.
(3). Resolving the level of ordinary skill in the pertinent art.
(4). Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chang and further in view of Pub. No. US 2015/0160285 A1 to Joh et al. (“Joh”).
Regarding claim 7, Chang does not disclose that each of the first electrical test and the second electrical test comprises use of a testing voltage between above 100 V and about 200 V.
Joh teaches a graph of set of pulses used for a first set of test conditions that includes coupling a voltage pulse generator to a drain terminal at a high voltage of 200 Volts (para [0048]) which is useful in observing a “soft switching” condition of a HFET (para [0048]).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the method of Chang by applying a voltage of 200 Volts for the first electrical test and the second electrical test to respective drain terminal of transistors in the build-up structure 128 and the core structure 150 of Chang in order to determine whether or not “soft switching” condition occurs.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 2.
Claims 3 and 4 are allowable for depending on the allowable claim 2.
Claim 8 is objected to for depending on a rejected base claim 1 and the intervening claim 7, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 and the intervening claim 7 or the base claim 1 is amended to include all of the limitations of claim 8 and the intervening
claim 7.
Independent claim 9 is allowed, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 9,
detaching the second build-up structure from the carrier substrate;
after the detaching, performing a second electrical test on the second build-up structure; and
after performing the first electrical test and the second electrical test, bonding the first build-up structure to the core structure.
Claims 10-16 are allowed, because they depend from the allowed independent claim 9.
Independent claim 21 is allowed, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 21,
detaching the first build-up structure from the carrier substrate;
attaching the first build-up structure to the core structure such that the metal features interface the plurality of contact pads; and
after the attaching, performing a third electrical test to the first build-up structure and the core structure.
Claims 22-24 are allowed, because they depend from the allowed independent claim 21.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pub. No. US 2023/0317529 A1 to Wang et al.
Pub. No. US 2022/0285233 A1 to Li et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL JUNG/Primary Examiner, Art Unit 2817 25 February 2026
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.