DETAILED ACTION
The present application is being examined under the pre-AIA first to invent provisions.
CONTINUED EXAMINATION UNDER 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/20/2025 has been entered.
RESPONSE TO ARGUMENTS
Applicant’s arguments with respect to claims 1-2, and 4-31 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
I. REJECTIONS BASED ON DOUBLE PATENTING
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,741,015. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the computer system described in claim 1 of the instant application are taught/suggested in claim 1 of the patented application (US Patent 11,741,015).
Claim 27 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 26 of U.S. Patent No. 11,741,015. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the computer system described in claim 1 of the instant application are taught/suggested in claim 26 of the patented application (US Patent 11,741,015).
II. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-2, and 4-26 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Macpherson (US Pub.: 2014/0082253) in view of Danilak (US Patent 7,623,134) Chen et al. (US Pub.: 2010/0118041), Kozakura (US Patent 5,724,581) and Herrell et al. (US Patent 5,301,287).
As per claim 1, Macpherson teaches/suggests a computer system, comprising: a first processor (Fig. 1, ref. 130); being coupled to the first processor (Fig. 1, ref. 130) and includes a first page table (Fig. 1, ref. 140), wherein the first page table includes one or more virtual address-to-physical address mappings for a first set of memory pages included in a plurality of memory pages that are accessible by the first processor via a virtual memory address space (Fig. 1-2; and [0015]-[0023]); a second processor (Fig. 1, ref. 135); and being coupled to the second processor (Fig. 1, ref. 135) and includes a second page table (Fig. 1, ref. 150), wherein the second page table includes one or more virtual address-to-physical address mappings for a second set of memory pages to which the second processor has access, operating with the one or more virtual address-to-physical address mappings included in the first page table and the one or more virtual address-to-physical address mappings included in the second page table (Fig. 1-2; and [0015]-[0023]).
Macpherson does not expressly teach the computer system comprising:
a system memory that is coupled accordingly; and
a local memory that is coupled accordingly, mapping included in the plurality of memory pages,
wherein the system memory also includes a page state directory that is a master page table for the virtual memory address space and includes virtual address-to-physical address mappings corresponding to.
Danilak teaches/suggests a computer system, comprising: a system memory (Fig. 1, ref. 120) that is coupled accordingly (Fig. 1; col. 2, l. 56 to col. 4, l. 67); and a local memory (Fig. 1, ref. 140) that is coupled accordingly (Fig. 1; and col. 2, l. 56 to col. 4, l. 67), wherein the system memory includes page table (e.g. associated with Fig. 1, ref. 122-123) for the virtual memory address space and includes virtual address-to-physical address mappings (Fig. 1; and col. 2, l. 56 to col. 4, l. 67).
Chen teaches/suggests a computer system, comprising: mapping included in the plurality of memory pages (e.g. associated with shared space accessed by CPU and GPU via corresponding page tables: [0015]-[0017]; [0040]), including a page state directory ([0043]) (Fig. 1; [0015]-[0025]; [0040]; and [0043]).
Kozakura teaches/suggests a computer system, comprising: page state data that is a master page table corresponding to (e.g. associated with backup page table being corresponding to current page table) (col. 3, ll. 28-55).
Herrell teaches/suggests a computer system, comprising: wherein the system memory also includes page state data (e.g. associated with shadow page table(s) being located in main memory) (col. 7, ll. 20-23).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Danilak’s storage architecture, Chen’s shared memory model, Kozakura’s backup page table, and Herrell’s shadow page table configuration into Macpherson’s computer system for the benefit of improving system performance (Danilak, col. 2, ll. 25-32), seamlessly sharing data structure between CPU and GPU (Chen, [0015]-[0017]), performing a failure recovery quickly (Kozakura, col. 3, ll. 53-55), and accessing data rapidly while maintaining security (Herrell, col. 2, ll. 59-61) to obtain the invention as specified in claim 1.
As per claim 2, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 1 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: wherein an application, when executed by the first processor, can access any memory page included in the plurality of memory pages via a pointer that points to different virtual addresses across the virtual memory address space (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23).
As per claim 4, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 1 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: wherein a page fault is issued when the first processor attempts to access a first memory page that is included in the plurality of memory pages but is not included in the first set of memory pages to which the first processor has access (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23).
As per claim 5, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 4 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: wherein the first memory page is migrated from the local memory to the system memory as part of a page fault sequence to provide the first processor with access to the first memory page (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23).
As per claim 6, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 5 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: wherein a first entry is generated for the first page table as part of the page fault sequence, wherein the first entry indicates that the first processor has access to the first memory page (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 7, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 5 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: wherein a first entry that is included in the page state directory and corresponds to the first memory page is updated as part of the page fault sequence to reflect that the first memory page is accessible to both the first processor and the second processor (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 8, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 5 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: wherein a first entry that is included in the page state directory and corresponds to the first memory page is updated as part of the page fault sequence to reflect that the first memory page is accessible to only the first processor (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 9, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 1 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: wherein a page fault is issued when the second processor attempts to access a first memory page that is included in the plurality of memory pages but is not included in the second set of memory pages to which the second processor has access (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23).
As per claim 10, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 9 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: wherein a first entry is generated for the second page table as part of a page fault sequence to provide the second processor with access to the first memory page, wherein the first entry indicates that the second processor has access to the first memory page (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23).
As per claim 11, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 10 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: wherein a first entry that is included in the page state directory and corresponds to the first memory page is updated as part of the page fault sequence to reflect that the first memory page is accessible to both the first processor and the second processor (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 12, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 11 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: wherein the first memory page is stored in the system memory (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 13, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 10 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: wherein a first entry that is included in the page state directory and corresponds to the first memory page is updated as part of the page fault sequence to reflect that the first memory page is accessible to only the second processor (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 14, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 13 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: wherein the first memory page is migrated from the system memory to the local memory as part of the page fault sequence (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 15, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 1 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: wherein the page state directory includes a separate entry for each memory page included in the plurality of memory pages, and each separate entry includes a virtual memory-to-physical memory mapping for a corresponding memory page included in the plurality of memory pages (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23).
As per claim 16, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 1 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: wherein the page state directory includes a first entry that corresponds to a first memory page included in the first set of memory pages to which the first processor has access, and an ownership state for the first memory page comprises a CPU-owned ownership state indicating that only the first processor has access to the first memory page (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 17, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 16 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: wherein the first memory page is stored in the system memory (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 18, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 1 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: wherein the page state directory includes a first entry that corresponds to a first memory page included in the first set of memory pages to which the first processor has access, and an ownership state for the first memory page comprises a CPU-shared ownership state indicating that both the first processor and the second processor have access to the first memory page (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 19, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 18 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: wherein the first memory page is also included in the second set of memory pages to which the second processor has access (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 20, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 18 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: wherein the first memory page is stored in the system memory (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 21, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 1 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: wherein the page state directory includes a first entry that corresponds to a first memory page included in the second set of memory pages to which the second processor has access, and an ownership state for the first memory page comprises a PPU-owned ownership state indicating that only the second processor has access to the first memory page (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 22, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 21 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: wherein the first memory page is stored in the local memory (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 23, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 1 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: wherein the page state directory includes a first entry that corresponds to a first memory page included in the second set of memory pages to which the second processor has access, and an ownership state for the for the first memory page comprises a PPU-shared ownership state indicating that both the first processor and the second processor have access to the first memory page (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 24, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 23 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: where the first memory page is stored in the local memory (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 25, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 1 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: wherein the first processor comprises a central processing unit, and the second processor comprises a parallel processing unit (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 26, Macpherson, Danilak, Chen, Kozakura, and Herrell teach/suggest all the claimed features of claim 25 above, where Macpherson, Danilak, Chen, Kozakura, and Herrell further teach/suggest the computer system comprising: wherein the parallel processing unit comprises a graphics processing unit (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; Kozakura, col. 3, ll. 28-55; and Herrell, col. 7, ll. 20-23), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
Claim 27-31 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Macpherson (US Pub.: 2014/0082253) in view of Danilak (US Patent 7,623,134) Chen et al. (US Pub.: 2010/0118041), and Kozakura (US Patent 5,724,581).
As per claim 27, Macpherson teaches/suggests a computer-implemented method for accessing memory pages, the method comprising: receiving a memory access request for a first memory page, wherein the memory access request includes a first virtual memory address (e.g. associated with first/second processor executing instruction stored at corresponding physical memory location via corresponding request including virtual memory address: Fig. 1; [0018]-[0019]), the first memory page is stored in a memory coupled to a first processor based on the first virtual memory address and a first page table associated with the first processor (e.g. associated with data/instruction stored at physical memory address of memory being accessed by first processor via corresponding page table that translates virtual memory address to physical memory address: Fig. 1; [0018]-[0019]), the first page table including one or more virtual address-to-physical address mappings for a first set of memory pages to which the first processor has access via a virtual memory address space (e.g. associated with first processor using corresponding page table for translating virtual memory address to physical memory address for accessing data/instruction: Fig. 1; [0018]-[0019]), or the first memory page is stored in a memory coupled to a second processor based on the first virtual memory address and a second page table associated with the second processor (e.g. associated with second processor using corresponding page table for translating virtual memory address to physical memory address for accessing data/instruction: Fig. 1; [0018]-[0019]), the second page table including one or more virtual address-to-physical address mappings for a second set of memory pages to which the second processor has access (e.g. associated with second processor using corresponding page table for translating virtual memory address to physical memory address for accessing data/instruction: Fig. 1; [0018]-[0019]); and to provide at least one of the first processor or the second processor access to the first memory page (e.g. associated with first/second processor using corresponding page table for translating virtual memory address to physical memory address for accessing data/instruction: Fig. 1; [0018]-[0019]), operating with the one or more virtual address-to-physical address mappings included in the first page table and the one or more virtual address-to-physical address mappings included in the second page table (Fig. 1-2; and [0015]-[0023]).
Macpherson does not teach the computer-implemented method comprising:
determining either that memory page is not stored in a system memory, or that the memory page is not stored in a local memory;
in response to determining that the first memory page is either not stored in the system memory or not stored in the local memory, generating a page fault; and
in response to the page fault, executing a page fault sequence using a page state directory to access to the memory page, wherein the page state director is a master page table for the virtual memory address space and include a plurality of virtual address-to-physical address mappings corresponding to.
Danilak teaches/suggests a computer-implemented method comprising: determining either that memory page is not stored in a system memory, or that the memory page is not stored in a local memory (e.g. associated with page not in system memory or not in frame buffer memory: col. 1, ll. 44-57); in response to determining that the first memory page is either not stored in the system memory or not stored in the local memory, generating a page fault (col. 1, ll. 44-57; col. 3, ll. 33-43; col. 4, ll. 12-60); and in response to the page fault, executing a page fault sequence to access to the memory page (col. 1, ll. 44-57; col. 3, ll. 33-43; col. 4, ll. 12-60), includes information that is a master page table (e.g. associated with Fig. 1, ref. 122-123) for the virtual memory address space and include mappings (e.g. associated with virtual-to-physical translation in the page table) (Fig. 1; col. 1, ll. 44-57; and col. 2, l. 56 to col. 4, l. 67).
Chen teaches/suggests a computer-implemented method comprising: using a page state directory to access, wherein the page state director operated accordingly ([0043]) (Fig. 1; [0015]-[0025]; [0040]; and [0043]).
Kozakura teaches/suggests a computer-implemented method comprising: page state data that is a master page table corresponding to (e.g. associated with backup page table being corresponding to current page table) (col. 3, ll. 28-55).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Danilak’s storage architecture, Chen’s shared memory model, and Kozakura’s backup page table into Macpherson’s computer system for the benefit of improving system performance (Danilak, col. 2, ll. 25-32), seamlessly sharing data structure between CPU and GPU (Chen, [0015]-[0017]), and performing a failure recovery quickly (Kozakura, col. 3, ll. 53-55) to obtain the invention as specified in claim 27.
As per claim 28, Macpherson, Danilak, Chen, and Kozakura teach/suggest all the claimed features of claim 27 above, where Macpherson, Danilak, Chen, and Kozakura further teach/suggest the computer-implemented method comprising: wherein an application executing on the first processor can access any memory page included in the first set of memory pages and the second set of memory pages via a pointer that points to different virtual addresses across the virtual memory address space (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 1, ll. 44-57; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; and Kozakura, col. 3, ll. 28-55), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 29, Macpherson, Danilak, Chen, and Kozakura teach/suggest all the claimed features of claim 27 above, where Macpherson, Danilak, Chen, and Kozakura further teach/suggest the computer-implemented method comprising: wherein the first memory page is stored in the system memory, and executing the page fault sequence comprises providing the second processor with access to the first memory page while the first memory page remains in the system memory (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 1, ll. 44-57; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; and Kozakura, col. 3, ll. 28-55), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 30, Macpherson, Danilak, Chen, and Kozakura teach/suggest all the claimed features of claim 27 above, where Macpherson, Danilak, Chen, and Kozakura further teach/suggest the computer-implemented method comprising: wherein the first memory page is stored in the system memory, and executing the page fault sequence comprises moving the first memory page from the system memory to the local memory (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 1, ll. 44-57; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; and Kozakura, col. 3, ll. 28-55), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 31, Macpherson, Danilak, Chen, and Kozakura teach/suggest all the claimed features of claim 27 above, where Macpherson, Danilak, Chen, and Kozakura further teach/suggest the computer-implemented method comprising: wherein the first memory page is stored in the local memory, and executing the page fault sequence comprises moving the first memory page from the local memory to the system memory (Macpherson, Fig. 1-2; [0015]-[0023]; Danilak, Fig. 1; col. 1, ll. 44-57; col. 2, l. 56 to col. 4, l. 67; Chen, Fig. 1; [0015]-[0025]; [0040]; [0043]; and Kozakura, col. 3, ll. 28-55), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
III. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-2 and 4-31 have received a first action on the merits and are subject of a first action non-final.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 February 20, 2026