DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3-4, 6-7, 9, 11, 16-17, 19, 26, 28-29, 31, 58, 75-79, and 88-89 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 4, 6-8, 10-13, 15-16, 18, 20-24, 42, and 59-72 of copending Application No. 18/154,353 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because applicant merely describes the first, second, and third contacts to be the source, drain, and gate contacts. Therefore, the reference application anticipates the instant application since the reference application fully encompasses the scope of the claims in the instant application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-4, 16, 58, 75-76, and 88-89 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US Publication No. 2020/0357729).
Regarding claim 1, discloses a power semiconductor package, comprising:
a first carrier submount (112)
a second carrier submount (104)
a plurality of semiconductor die (101/102), each semiconductor die (102) of the plurality of semiconductor die having a first surface (134) and an opposing second surface (139)
for each semiconductor die of the plurality of semiconductor die (101/102)
the first surface (134) is directly coupled to the first carrier submount (112)
the second surface (139) is directly coupled to the second carrier submount (104)
Regarding claim 3, discloses:
each semiconductor die (101/102) of the plurality of semiconductor die comprises a first contact (125/131) on the first surface and a second contact (128/138) on the second surface (139)
the first carrier submount (112) comprises one or more conductive patterns (114/116)
for each semiconductor die (101/102) of the plurality of semiconductor die:
the first contact (122/131) is directly coupled to at least one of the one or more conductive patterns (114/116) of the first carrier submount (112)
the second contact (128/138) is directly coupled to the second carrier submount (104)
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Regarding claim 4, Kim discloses each semiconductor die (101/102) further comprises a third contact (125) on the first surface, and wherein, for each semiconductor die (101/102) of the plurality of semiconductor die: the third contact (125) is directly coupled to at least one of the one or more conductive patterns (114/116) of the first carrier submount (112); and the first contact and the third contact are coupled to different conductive patterns of the first carrier submount (112) (Figure 12 shows multiple element 125 on 101 and 102 are couples to different connections on 112).
Regarding claim 16, Kim discloses the first carrier submount comprises: a first conductive layer (114/116); a second conductive layer (118); and an insulating layer (112) between the first conductive layer (114/116) and the second conductive layer (118).
Regarding claim 58, Kim discloses a power semiconductor package, comprising:
a carrier submount (112) comprising one or more conductive patterns (114/116)
a first lead frame (104) comprising one or more conductive leads (802)
a second lead frame (108) comprising one or more conductive leads (108/109)
a first semiconductor die (102) having a first surface directly coupled to the carrier submount (112) and an opposing second surface directly coupled to the first lead frame (104), the first semiconductor die further comprising:
a source contact (128/138) on the first surface coupled to at least one of the one or more conductive patterns (114/116) of the carrier submount (112)
a gate contact on the first surface coupled to at least one of the one or more conductive patterns (114/116) of the carrier submount (paragraph 37)
a drain contact (108) on the second surface coupled to at least one of the one or more conductive leads (108/109) of the first lead frame (108)
a second semiconductor die (101) having a first surface directly coupled to the carrier submount (112) and an opposing second surface directly coupled to the second lead frame, the second semiconductor die further comprising:
a source contact (128/138) on the first surface coupled to at least one of the one or more conductive patterns of the carrier submount (112) and to at least one of the one or more conductive leads of the first lead frame (104)
a gate contact on the first surface coupled to at least one of the one or more conductive patterns of the carrier submount (112)
a drain contact (108) on the second surface coupled to at least one of the one or more conductive leads of the second lead frame (108)
Regarding claim 75, Kim discloses a power semiconductor package, comprising:
a first carrier submount (112), the first carrier submount comprising:
a first conductive layer (114/116)
a second conductive layer (118)
an insulating layer (112) between the first conductive layer (114/116) and the second conductive layer (118)
a second carrier submount (104)
a semiconductor die (102), the semiconductor die having a first surface and an opposing second surface
wherein the first conductive layer (114/116) and the second conductive layer (118) comprise different conductive patterns (Figure 13)
Regarding claim 76, discloses the first conductive layer (114/116) comprises a source pattern (108); and the second conductive layer (118) comprises a gate pattern (paragraph 37).
Regarding claim 88, Kim discloses the first carrier submount (112) provides a first thermally conductive path for the plurality of semiconductor die, and the second carrier submount (104) provides a second thermally conducive path for the plurality of semiconductor die (paragraph 35).
Regarding claim 89, Kim discloses an encapsulating portion (120) at least partially around the first carrier submount (112) and the second carrier submount (104), the encapsulating portion forming a housing for the power semiconductor package, wherein the first thermally conductive path and the second thermally conductive path extend towards opposing sides of the housing (Figure 1; paragraph 35).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-7, 9, 11, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Publication No. 2020/0357729) in view of Maldo et al. (US Publication No. 2022/0020740).
Regarding claim 6, Kim discloses the limitations as discussed in the rejection of claim 4 above. Kim also discloses the first contact (125 left) is a source contact (128/138). Kim does not disclose the second contact is a drain contact; and the third contact is at least one of a gate contact or a kelvin contact. However, Maldo discloses drain (936), source (938), and gate (940) on the same side of a die on a submount (944) (paragraph 111). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the die contacts of Kim to be formed on the same side to a first submount, as taught by Maldo, since improve creepage distance, thereby minimizing failures (paragraphs 71-73).
Regarding claim 7, Kim discloses each semiconductor die of the plurality of semiconductor die (101/102) are coupled to a common source terminal (104), the second carrier submount (104) comprises a plurality of conductive leads (106), and each drain contact (108) of the plurality of semiconductor die is coupled to a different conductive lead of the plurality of conductive leads (Figure 12).
Regarding claim 9, Maldo discloses each semiconductor die of the plurality of semiconductor die are coupled to a common drain terminal, each source contact of the plurality of semiconductor die is coupled to a different conductive pattern of the one or more conductive patterns (Figures 9-10; paragraphs 71-74).
Regarding claim 11, Maldo discloses each semiconductor die of the plurality of semiconductor die are coupled to a common gate terminal (Figures 9-10; paragraphs 75-77).
Regarding claim 17, Kim discloses the limitations as discussed in the rejection of claim 16 above. Kim also discloses the first conductive layer (114/116) and the second conductive layer (118) comprise different conductive patterns (Figure 13). Kim does not disclose the first conductive layer comprises a source pattern and a gate pattern. However, Maldo discloses drain (936), source (938), and gate (940) on the same side of a die on a submount (944) (paragraph 111). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the die contacts of Kim to be formed on the same side to a first submount, as taught by Maldo, since improve creepage distance, thereby minimizing failures (paragraphs 71-73).
Claims 19, 26, 29, and 77-79 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Publication No. 2020/0357729) in view of Stella et al. (US Publication No. 2022/0199563).
Regarding claim 19, Kim discloses the first conductive layer (114/116) comprises a source pattern (108); and the second conductive layer (118) comprises a gate pattern (paragraph 37). Kim does not disclose the power semiconductor further comprises a plurality of vias extending through the insulating layer connecting the second conductive layer to the plurality of semiconductor die. However, Stella discloses vias (32) formed through an insulating layer (106), connecting a conductive layer (33) to the die (2) (Figure 12). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the layers of Kim to include these connection vias, as taught by Stella to improve thermal dissipation from both sides of the device (paragraph 139).
Regarding claim 26, Kim discloses the limitations as discussed in the rejection of claim 1 above. Kim is silent regarding the wide band gap semiconductor is silicon carbide. However, Stella discloses a wide band gap semiconductor that is silicon carbide (paragraph 5). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the semiconductor die of Kim to be made of silicon carbide, as taught by Stella, since for their use in high voltage/high power applications that can allow for fast power conversion and rapid switching (paragraphs 2-3).
Regarding claim 29, Stella discloses the power semiconductor die comprises a silicon carbide-based MOSFET (paragraph 5).
Regarding claim 77, Kim discloses the limitations as discussed in the rejection of claim 76 above. Kim does not disclose the first carrier submount further comprises a via extending through the insulating layer connecting the second conductive layer to the semiconductor die. However, Stella discloses vias (32) formed through an insulating layer (106), connecting a conductive layer (33) to the die (2) (Figure 12). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the layers of Kim to include these connection vias, as taught by Stella to improve thermal dissipation from both sides of the device (paragraph 139).
Regarding claim 78, Kim discloses the semiconductor die (102) comprises a source contact (S) on the first surface and a drain contact (D) on the second surface (Figure 12).
Regarding claim 79, Kim discloses the semiconductor die (102) further comprises a gate contact on the first surface (paragraph 37).
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Publication No. 2020/0357729) in view of Broll et al. (US Publication No. 2023/0063259).
Regarding claim 28, Kim discloses the limitations as discussed in the rejection of claim 1 above. Kim does not disclose the power semiconductor package does not include any wire bonds. However, Broll discloses optionally using wire bonds or metal clips (paragraph 27). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Kim to avoid using wire bonds, as taught by Broll, since it can improve current carrying capacity to use metal clips or bond pads (paragraphs 1-2).
Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Publication No. 2020/0357729) in view of Seal et al. (US Publication No. 2022/0238426).
Regarding claim 31, Kim discloses the limitations as discussed in the rejection of claim 1 above. Kim is silent regarding the power semiconductor die comprises a silicon carbide-based Schottky diode. However, Seal discloses a silicon carbide-based Schottky diode (paragraph 2). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the semiconductor die of Kim to comprise a SiC Schottky diode, as taught by Seal, for its high reliability and wide applications in high voltage devices (paragraphs 2-5).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm.
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/N.R.P/ 3/13/2026Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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