Prosecution Insights
Last updated: April 19, 2026
Application No. 18/457,523

REINFORCEMENT STRUCTURES FOR MULTI-DIE SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME

Non-Final OA §102§103
Filed
Aug 29, 2023
Examiner
PARTHASARATHY, ROHIT
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Limited
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
3y 4m
To Grant
99%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allow Rate
21 granted / 23 resolved
+23.3% vs TC avg
Moderate +13% lift
Without
With
+13.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
31 currently pending
Career history
54
Total Applications
across all art units

Statute-Specific Performance

§103
56.6%
+16.6% vs TC avg
§102
24.3%
-15.7% vs TC avg
§112
17.6%
-22.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 23 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Option 2 in Group 1, Option 1 in Group 2, Option 1 in Group 3, and Option 1 in Group 4 in the reply filed on 12/05/2025 is acknowledged. Claims 1-20 remain pending. Claims 6, 8-10, 15-16, and 19-20 are withdrawn. Claim Objections Claim 14 is objected to because of the following informalities: the claim states in part “…wherein the reinforcement structure is coupled only to a first vertical surface of the first semiconductor die and only to a second vertical surface of the second semiconductor die.” In the view of the Examiner, the clam should state “…wherein the reinforcement structure is coupled only to a first vertical surface of the of the first semiconductor die and Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2, 4-5, and 7 are rejected under 35 U.S.C. 102a1 as being anticipated by US20210384096A1 (Lee). Regarding Claim 1, Lee discloses a semiconductor package (Figs. 1 and 2A, el. 300, Paras. [0028] and [0040]), comprising: a package substrate (Fig. 1, el. 100, Para. [0029]); a first semiconductor die (Fig. 2A, el. 130, Para. [0041]) electrically and mechanically coupled to the package substrate (Para. [0029]); a second semiconductor die (Fig. 2A, el. 140, Para. [0041]) electrically and mechanically coupled to the package substrate (Para. [0029]); and a reinforcement structure (Fig. 2A, el. 160, Para. [0053]) mechanically coupled to at least a first vertical surface of the first semiconductor die and a second vertical surface vertical surface of the second semiconductor die (see Fig. 2A, where 160 touches both the first and second die); wherein the reinforcement structure surrounds less than an entirety of the first semiconductor die and the second semiconductor die (see Fig. 2A where 160 is only on one side of each of the first and second semiconductor dies). Regarding Claim 2, Lee discloses the semiconductor package of claim 1, further comprising an underfill material (Fig. 2A, els. 113 and 119, Para. [0052]) formed between a top surface of the package substrate and bottom surfaces of the first semiconductor de and the second semiconductor die (Fig. 2A, Para. [0052]). Regarding Claim 4, Lee discloses the semiconductor package of Claim 1, wherein the reinforcement structure comprises a polymer material (Para. [0058]) located in a space between the first semiconductor die and the second semiconductor die (Fig. 2A). Regarding Claim 5, Lee discloses the semiconductor package of Claim 4, wherein a first length of the reinforcement structure is less than or equal to a second length of the first semiconductor die and the second semiconductor die (Figs. 1 and 2A, Para. [0035]). Regarding Claim 7, Lee discloses the semiconductor package of claim 4, wherein a first thickness of the reinforcement structure is less than or equal to a second thickness of the first semiconductor die and the second semiconductor die (Para. [0054]). Claims 11 and 13-14 are rejected under 35 U.S.C. 102a1 as being anticipated by Lee. Regarding Claim 11, Lee discloses a semiconductor package (Figs. 1 and 2A, el. 300, Paras. [0028] and [0040]), comprising: a package substrate (Fig. 1, el. 100, Para. [0029]); a first semiconductor die (Fig. 2A, el. 130, Para. [0041]) electrically and mechanically couples to the package substrate (Para. [0029]); a second semiconductor die (Fig. 2A, el. 140, Para. [0041]) electrically and mechanically coupled to the package substrate (Para. [0029]); and a reinforcement structure (Fig. 2A, el. 160, Para. [0053]) formed in a vertical space between the first semiconductor die and the second semiconductor die (Figs. 1 and 2A, Para. [0053]), wherein the reinforcement structure comprises a first width that is less than or equal to a second width of the first semiconductor die and the second semiconductor die (Figs. 1 and 2A, Para. [0053]). Regarding Claim 13, Lee discloses the semiconductor package of claim 11, wherein the reinforcement structure further comprises a polymer matrix composite material (Para. [0058]) Regarding Claim 14, Lee discloses the semiconductor package of claim 11, wherein the reinforcement structure is coupled only to a first vertical surface of the first semiconductor die and only to a second vertical surface of the second semiconductor die (Figs. 1 and 2A, Para. [0035] – Para. [0029] states that the semiconductor package 300 includes at least two semiconductor chips. In the embodiment where chip 150 is eliminated, there will be only two semiconductor chips, 130 and 140, and only one gap between them, which the reinforcement structure can fill, thus meeting this limitation.) Claim 17 is rejected under 35 U.S.C. 102a1 as being anticipated by Lee. Regarding Claim 17, Lee discloses a method of forming a semiconductor package (see Figs. 1 and 2A – where a method can be inferred from the resulting structure), comprising: attaching a first semiconductor die (Fig. 2A, el. 130, Para. [0041]) to a package substrate (Fig. 1, el. 100, Para. [0029]) such that the first semiconductor die is electrically and mechanically coupled to the package substrate (Para. [0029]); attaching a second semiconductor die (Fig. 2A, el. 140, Para. [0041]) to the package substrate such that the second semiconductor die is electrically and mechanically coupled to the package substrate (Para. [0029]); and forming a reinforcement structure (Fig. 2A, el. 160, Para. [0053]) mechanically coupled to at least a first vertical surface of the first semiconductor die and a second vertical surface of the second semiconductor die (see Fig. 2A, where 160 touches both the first and second die); such that the reinforcement structure surrounds less than an entirety of the first semiconductor die and the second semiconductor die (see Fig. 2A where 160 is only on one side of each of the first and second semiconductor dies). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lee. Regarding Claim 3, Lee discloses the semiconductor package of claim 2, wherein the reinforcement structure comprises a polymer matrix composed material (Para. [0058]). Lee does not disclose that the polymer matrix material has a greater modulus than the underfill material. Lee does disclose that the polymer material can include a filler material, such as aluminum oxide (Para. [0058]). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to include enough filler material, such as aluminum oxide, in the polymer material such that the resulting modulus of the polymer and filler is higher than the modulus of the underfill. First, it is known that adding filler material, such as aluminum oxide, increases the modulus of elasticity of a polymer, and adding more filler further increases the modulus. Second, the amount of filler, and the resulting modulus, is a product of optimization. A person of ordinary skill in the art, by simply varying the amount of filler, would have a reasonable expectation of success in finding an optimal range that has the desired amount of stiffness relative to the underfill material (MPEP2144.05 II). Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lee. Regarding Claim 12, Lee discloses the semiconductor package of Claim 11, further comprising an underfill material (Fig. 2A, els. 113 and 119, Para. [0052]) formed between a top surface of the package substrate and bottom surfaces of the first semiconductor de and the second semiconductor die (Fig. 2A, Para. [0052]). Lee does not disclose that the reinforcement structure comprises a greater modulus than the underfill material. Lee does disclose that the polymer material of the reinforcement structure can include a filler material, such as aluminum oxide (Para. [0058]). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to include enough filler material, such as aluminum oxide, in the polymer material of the reinforcement structure such that the resulting modulus of the polymer and filler is higher than the modulus of the underfill. First, it is known that adding filler material, such as aluminum oxide, increases the modulus of elasticity of a polymer, and adding more filler further increases the modulus. Second, the amount of filler, and the resulting modulus, is a product of optimization. A person of ordinary skill in the art, by simply varying the amount of filler, would have a reasonable expectation of success in finding an optimal range that has the desired amount of stiffness relative to the underfill material (MPEP2144.05 II). Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lee. Regarding Claim 18, Lee discloses the method of Claim 17, further comprising forming an underfill material (Fig. 2A, els. 113 and 119, Para. [0052]) between a top surface of the package substrate and bottom surfaces of the first semiconductor de and the second semiconductor die (Fig. 2A, Para. [0052]). Lee does not disclose that the underfill material comprises a modulus that is less than that of the reinforcement structure. Lee does disclose that the polymer material of the reinforcement structure can include a filler material, such as aluminum oxide (Para. [0058]). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to include enough filler material, such as aluminum oxide, in the polymer material of the reinforcement structure such that the resulting modulus of the polymer and filler is higher than the modulus of the underfill. First, it is known that adding filler material, such as aluminum oxide, increases the modulus of elasticity of a polymer, and adding more filler further increases the modulus. Second, the amount of filler, and the resulting modulus, is a product of optimization. A person of ordinary skill in the art, by simply varying the amount of filler, would have a reasonable expectation of success in finding an optimal range that has the desired amount of stiffness relative to the underfill material (MPEP2144.05 II). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROHIT PARTHASARATHY whose telephone number is (571)272-2572. The examiner can normally be reached Monday-Friday 8:30a-5p. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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Prosecution Timeline

Aug 29, 2023
Application Filed
Dec 16, 2025
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
99%
With Interview (+13.3%)
3y 4m
Median Time to Grant
Low
PTA Risk
Based on 23 resolved cases by this examiner. Grant probability derived from career allow rate.

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