DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Application
In response to Office action dated 10/07/2025 (“10-07-25 OA”), Applicant amended title and filed remarks and filed a certified English language translation of the Japanese foreign priority document in reply dated 01/26/2026 (“01-26-26 Reply”).
Response to Arguments
Applicant’s amendments to title overcome the objection to specification as set forth under line item number 1 of the 10-07-25 OA.
Noted in line item number 2 of the 10-07-25 OA that there are trade names or marks used in commerce mentioned in present application.
Applicant’s certified English language translation of the present application’s Japanese foreign priority document overcomes the Chen reference as a 102(a)(1) dated reference used in an obviousness rejection under 35 USC 103.
Applicant’s remarks in page 8 of the 01-26-26 Reply attempts to overcome the Chen reference as a 102(a)(2) dated reference used in an obviousness rejection under 35 USC 103. Specifically, frame and reel numbers are referenced by Applicant along with the statement, “Applicant respectfully submits that both the instant application and the Chen et al. reference are commonly assigned to Disco Corporation.”
With respect to frame and reel numbers: see MPEP 2154.02(c); “In order to comply with the rules, a statement is required regardless of any assignment information that may have been recorded in the assignment database maintained by the Office.” (bolded for emphasis).
With respect to the required statement: To overcome a AIA 35 U.S.C. 102(a)(2) rejection via common ownership, the applicant must file a statement asserting that the subject matter of the reference and the claimed invention were commonly owned or under an obligation of assignment to the same person/entity no later than the effective filing date of the claimed invention. This exception falls under 35 U.S.C. 102(b)(2)(C). (bolded for emphasis).
(ii) as applied to (i): the effective filing date due to perfecting foreign priority of present application is 09/05/2022; whereas the frame and reel quoted by Applicant for Assignment is dated 08/29/2023 that is after the 09/05/2022 date.
Office appreciates Applicant’s attempt to prove with evidence the required statement, however no evidence is required and only the specific statement above is expressly required. The statement is taken on face value as truthful unless independent evidence raises doubt as to the veracity of such a statement1.
To overcome the Chen reference as a 102(a)(2) dated reference please respond in an after-final amendment with the required statement, using the same language as bolded above, without corroborating evidence so as to proceed to allowance.
Since the Chen reference as a 102(a)(2) dated reference is not currently overcome, the previous prior art rejections from the 10-07-25 OA are copied below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0020620 A1 to Chen et al. (“Chen”) in view of US 2017/0162420 A1 to Morikazu.
Regarding independent claim 1, Chen teaches a method of manufacturing (see title) laminated device chips (device chips as mentioned in paragraphs 0005 and 0094), comprising:
a preparing step of preparing a first device wafer 11 (“first device wafer”; Figure 1A; paragraph 0036) having a plurality of areas 19 (“devices”; Figure 1A; paragraph 0038) demarcated in a face side 11a (“front surface”; Figure 1A; paragraph 0037) thereof by a grid of first projected dicing lines 15/15a/15b (“planned dividing lines”; Figure 1A) established therein and containing respective first devices 19, a second device wafer 21 (“second device wafer”; Figure 1A; paragraph 0036) having a plurality of areas 19 (“devices”; Figures 1A and 5; paragraph 0038. See paragraph 0036, “Description will first be made of a first device wafer 11 (see FIGS. 1A and 1B) and a second device wafer 21 (see FIG. 5). However, both have substantially a same shape, and therefore description will be made of the first device wafer 11”) demarcated in a face side thereof by a grid of second projected dicing lines 15 established therein and containing respective second devices 19, and a support substrate 33 (“provisional fixing substrate”; Figure 4A; paragraph 0044);
an integrating step S20 (“provisional fixing step”; Figure 2) of affixing (see paragraph 0044: “the provisional fixing substrate 33 in a disk shape is fixed to the front surface 11a side via the provisional adhesive layer 35 ]provisional fixing step S20]”; Figure 4a and Figure 2) the support substrate 33 to the face side 11a of the first device wafer 11 to integrally combine the support substrate 33 and the first device wafer 11 with each other;
after the integrating step S20, a thinning step S30 (“thinning step”; Figure 2) of processing the first device wafer 11 from a reverse side 11b (“back surface”; Figure 4A and Figure 2; paragraph 0045) thereof to thin down (see paragraphs 0044-50) the first device wafer 11 to a predetermined thickness (i.e., the end thickness needed after thinning);
an affixing step S44 (see Figure 5 and paragraph 0055, “At this time, the front surface 11a and the front surface 21a are located at an approaching distance 39b from each other to such a degree as to be able to be imaged by the microscope camera unit 32 at the same time.” Also see Figure 9A and paragraph 0064, “The first device wafer 11 and the second device wafer 21 are thereby bonded and fixed to each other”) of affixing the first device wafer 11 as thinned S30 to the second device wafer 21;
a peeling step S50 (“peeling step”; Figure 2) of peeling (see Figure 9B and paragraph 0065, “After the lowering and fixing step S44, the provisional fixing substrate 33 is peeled off from the front surface 11a side by decreasing the adhesive force of the provisional adhesive layer 35 [peeling step S50]”) the support substrate 33 from the first device wafer 11 as thinned S30; and
a dividing step (Paragraph 0005 along with alignment of the dividing lines 15 between 11 and 21 as best illustrated in adjustment in 17b direction of 17a direction with respect to paragraphs 0058 and 0060, Figure 7A-7B and Figures 8A-8B, respectively. As such, even though no actual dividing is taught; this is made obvious over Chen by the lamination of aligned devices 19 between 11 and 21 along with alignment of the dividing lines 15 between 11 and 21. This is also made obvious because Chen mentions chips. The dividing/dicing lines are made to be cut through both substrates thereby making laminated chips) of dividing the second device wafer 21 along the second projected dicing lines 15 into a plurality of individual laminated device chips (11+21 together between aligned dividing lines 15).
Chen expressly teaches or makes obvious all the method steps outlined supra except a claimed cutting step that is between the claimed thinning step and the claimed fixing step of laminating the two device wafers together.
Morikazu teaches in Figure 1A of device wafer 2 with devices 21 each separated by a grid of dividing lines 21. Morikazu further teaches of a thinning step in Figure 2 that requires device wafer 2 to be supported by a supporting substrate 3 that is mounted on the device 21 side of device wafer 2. Morikazu also teaches in Figures 3A-3C, paragraphs 0024 and 0026 that device wafer 2 has a cut-groove forming step along grid dividing lines 21. A later step also has device wafer 2 mounted on a tape T that then has support wafer 3 peeled off as per Figure 6, paragraph 0039.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to recognize combining Morikazu’s cut-groove step with Chen’s invention would have been beneficial in order to provide an easier final dividing step for Chen’s invention because the dividing lines for the first device wafer as provided by Morikazu would have already been cut thereby making the final division of the laminated chips easier for Chen and also making the alignment between the previously planned division lines easier between the two laminated wafers.
Regarding claim 2, Chen teaches that the integrating step includes affixing the support substrate 33 to the first device wafer 11 with an adhesive 35 (“provisional adhesive layer”; Figure 4A; paragraph 0044), and
the peeling step S50 includes reducing bonding strength (see Figure 9B and paragraph 0065: “In a case where the provisional adhesive is an ultraviolet curable resin, for example, the provisional fixing substrate 33 is peeled off after the adhesive force is reduced by irradiating the front surface 11a side with ultraviolet rays”) of the adhesive 35 and peeling off the support substrate 33 from the first device wafer 11.
Allowable Subject Matter
Claims 3-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 3 contains allowable subject matter, because the closest art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 3, wherein the integrating step includes affixing the support substrate to the first device wafer with an adhesive, the cutting step includes fully cutting the support substrate together with the first device wafer into a plurality of device chips, the affixing step includes placing the device chips on the second device wafer from the first device wafer side and thereafter affixing a tape to the support substrate, and the peeling step includes applying a laser beam through the tape and the support substrate to the adhesive to reduce bonding strength of the adhesive and peeling off the support substrate together with the tape from the first device wafer.
Claim 4 contains allowable subject matter, because the closest art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 4, the integrating step includes affixing the support substrate to the first device wafer with a thermoplastic adhesive, the cutting step includes fully cutting the support substrate together with the first device wafer into a plurality of device chips, the affixing step includes placing the device chips on the second device wafer from the first device wafer side and thereafter affixing a retrieval substrate to the support substrate with a thermosetting adhesive, and the peeling step includes heating the thermoplastic adhesive to reduce bonding strength of the thermoplastic adhesive and peeling off the support substrate together with the retrieval substrate from the first device wafer.
Claim 5 contains allowable subject matter, because the closest art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 5, after the peeling step and before the dividing step, encapsulating areas that do not overlap the first device wafer and that overlap the second device wafer with an encapsulating resin.
With respect to dependent claims 3-5, the combination of Chen with Morikazu falls apart due to the limitations of each respective claim.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN P DULKA whose telephone number is (571)270-7398. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ELISEO RAMOS-FELICIANO can be reached at (571)272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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07 March 2026
/John P. Dulka/Primary Examiner, Art Unit 2817
1 See MPEP 2154.02(c): A clear and conspicuous statement by the applicant (or the applicant's representative) that the claimed invention of the application under examination and the subject matter disclosed in the U.S. patent document applied as prior art were owned by the same person or subject to an obligation of assignment to the same person not later than the effective filing date of the claimed invention will be sufficient to establish that the AIA 35 U.S.C. 102(b)(2)(C) exception applies. Likewise, when relying on the provisions of pre-AIA 35 U.S.C. 103(c), the applicant (or the applicant's representative) can provide a similar statement required to disqualify the cited prior art. The applicant may present supporting evidence such as copies of assignment documents, but is not required to do so. Furthermore, the Office will not request corroborating evidence in the absence of independent evidence which raises doubt as to the veracity of such a statement. The statement under AIA 35 U.S.C. 102(b)(2)(C) will generally be treated by Office personnel analogously to statements made under pre-AIA 35 U.S.C. 103(c). See MPEP § 2146.02, subsection II. In order to comply with the rules, a statement is required regardless of any assignment information that may have been recorded in the assignment database maintained by the Office.