DETAILED ACTION
This Office Action is responsive to the Applicant’s communications filed 29 August 2023 and 3 June 2026. In view of this communication, claims 1-15 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Claims 8-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3 June 2026.
Claim Objections
Claims 4-5 are objected to because of the following informalities: Claims 4 and 5 recite “each of the differential lines comprising” and should instead recite “each of the differential lines comprises.” Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Farkas et al. (US 20210321510 A1), hereinafter referred to as Farkas et al.
Regarding claim 1, Farkas et al. teaches a circuit board, comprising:
a first circuit layer (460) (Fig. 4d and paragraph 25: power layers 460 in the central layers of the circuit board 480);
a second circuit layer (460) (Fig. 4d and paragraph 25: the second circuit layer corresponds to uppermost reference conductor layer 460);
a third circuit layer (460) (Fig. 4d and paragraph 25: the third circuit layer corresponds to lowermost reference conductor layer 460), wherein the first circuit layer (460) is disposed between the second circuit layer (460) and the third circuit layer (460) (Fig. 3d and paragraph 25: power layers 460 are located between the upper and lower conductor layers 460);
a first differential line group (414) disposed between the first circuit layer (460) and the second circuit layer (460) (Fig. 4d and paragraph 25: the conductor traces 411, 413 that are connected to the terminal 414 are located on a layer of the PCB between upper circuit layer 460 and the central power layers 460);
a second differential line group (416) disposed between the first circuit layer (460) and the third circuit layer (460) (Fig. 4d and paragraph 25: the conductor traces 411, 413 that are connected to the terminal 416 are located on a layer of the PCB between lower circuit layer 460 and the central power layers 460);
a third differential line group (410) disposed between the first circuit layer (460) and the second circuit layer (460) (Fig. 4d and paragraph 25: the conductor traces 411, 413 that are connected to the terminal 410 are located on a layer of the PCB between upper circuit layer 460 and the central power layers 460); and
a fourth differential line group (418) disposed between the first circuit layer (460) and the third circuit layer (460) (Fig. 4d and paragraph 25: the conductor traces 411, 413 that are connected to the terminal 418 are located on a layer of the PCB between lower circuit layer 460 and the central power layers 460),
wherein the first differential line group (414) has a first orthogonal projection on the first circuit layer (460), the second differential line group (416) has a second orthogonal projection on the first circuit layer (460), the third differential line group (410) has a third orthogonal projection on the first circuit layer (460), and the fourth differential line group (418) has a fourth orthogonal projection on the first circuit layer (460), wherein the first orthogonal projection separates from the third orthogonal projection, and the second orthogonal projection separates from the fourth orthogonal projection (see Fig. 4d: each conductor layer where the traces 411, 413 of each respective differential pair has a different distance from the central power layers 460, such that their orthogonal projections are separated),
wherein there is a first distance between the first differential line group (414) and the first circuit layer (460), there is a second distance between the second differential line group (416) and the first circuit layer (460), there is a third distance between the third differential line group (410) and the first circuit layer (460), and there is a fourth distance between the fourth differential line group (418) and the first circuit layer (460), wherein the first distance is less than the third distance, and the second distance is less than the fourth distance (see Fig. 4d: the traces 411, 413 corresponding to terminals 414 and 416 are located closer to the central power layers 460 than the traces 411, 413 corresponding to terminals 410 and 418, respectively).
Regarding claim 2, Farkas et al. teaches the circuit board of claim 1, wherein each of the first differential line group (414), the second differential line group (416), the third differential line group (410), and the fourth differential line group (418) comprises two differential lines (411, 413) (paragraph 25: each differential pair comprises traces 411 and 413).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Farkas et al. in view of Jia (CN 210836905 U), hereinafter referred to as Jia.
Regarding claim 4, Farkas et al. teaches the circuit board of claim 2, but does not teach that each of the differential lines comprising: a conductive structure, wherein the conductive structure is made of graphene; and an insulating structure surrounding the conductive structure, wherein the insulating structure is made of graphene oxide.
Jia does teach that each of the differential lines may comprise a conductive structure, wherein the conductive structure is made of graphene; and an insulating structure surrounding the conductive structure, wherein the insulating structure is made of graphene oxide (Jia page 2, final paragraph and page 4, fifth paragraph: a conductive trace comprising graphene is surrounded by insulating layers comprising graphene oxide).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the differential lines of Farkas et al. from a graphene conductive structure and graphene oxide insulating structure as taught by Jia because the structure disclosed by Jia harnesses the excellent conductive properties of graphene and provides excellent adhesion of the insulating layer to the conductor (see Jia page 2, final paragraph and page 4, sixth paragraph).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Farkas et al. in view of Lin et al. (US 20240363520 A1), hereinafter referred to as Lin et al.
Regarding claim 7, Farkas et al. teaches the circuit board of claim 1, but does not teach a sealing member disposed on the second circuit layer, wherein the second circuit layer comprises a hole, the hole disposed above the third differential line group, and the sealing member covers the hole.
Lin et al. does teach a sealing member disposed on the second circuit layer, wherein the second circuit layer comprises a hole, the hole disposed above the third differential line group, and the sealing member covers the hole (Lin et al. Fig. 2A and paragraph 28: a liquid metal carrier array is provided in connection with pads and corresponding circuitry 223 and capping 226 to seal the holes that contain the liquid metal 224).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a sealing member as taught by Lin et al. on the second circuit layer of Farkas et al. because the LMCA of Lin et al., which requires the sealing member, allows for easy assembly and replacement of features while Lin et al.’s seal prevents moisture ingress (Lin et al. paragraphs 2-3).
Allowable Subject Matter
Claims 3 and 5-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in the claim a liquid metal structure encapsulating each of the differential lines.
Conclusion
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/JOHN B FREAL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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