Prosecution Insights
Last updated: July 17, 2026
Application No. 18/457,840

DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME

Final Rejection §103§112
Filed
Aug 29, 2023
Priority
Sep 13, 2022 — RE 10-2022-0114748
Examiner
REAMES, MATTHEW L
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
2 (Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
844 granted / 1097 resolved
+8.9% vs TC avg
Strong +18% interview lift
Without
With
+18.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
45 currently pending
Career history
1123
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
75.2%
+35.2% vs TC avg
§102
5.2%
-34.8% vs TC avg
§112
11.5%
-28.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1097 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-4, 8-9, 11-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. a. As to claim 1 the recitation of level is unclear. Applicant has not set forth set forth antecedent basis for level. The office will interpret the claim to mean the device comprising a plurality of laminations levels. And the pad electrode is at a different lamination level then the alignment electrodes. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-4, 8-9, and 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choung 20220157856 in view of Kim 20210313498. a. As to claim 1, Choung teaches display device comprising: a substrate including a display area (Figure 5 DPA) and a pad area (PDA); a circuit element layer on the substrate (DTR); wherein the circuit element layer comprises: a thin film transistor in the display area (paragraph 113); and a pad electrode in the pad area (141-143), and a pad upper electrode including a first opening exposing the pad electrode in the pad area (item 145 with opening exposing 143. Choung teaches the display maybe inorganic (paragraph 55). Choung does not explicitly teach an alignment electrode on the circuit element wherein the alignment electrode layer comprises: a first alignment electrode and a second alignment electrode spaced from each other in the display area and wherein a light emitting element is located in a space between the first alignment electrode and the second alignment electrode that are spaced from each other. Kim teaches a substrate including a display area (figure 23 DPA) a pad area (PDA); a circuit element layer on the substrate (ACT1); and an alignment electrode layer (21_3 and 22_3 (paragraph 117 and 136) on the circuit element layer (21_3 and 22_3 are on ACT1), wherein the circuit element layer comprises: tft (paragraph 90) in the display area (ACT1); wherein the alignment electrode layer comprises: a first alignment electrode and a second alignment electrode spaced from each other in the display area (items 21_3 and 22_3); and wherein a light emitting element is located in a space between the first alignment electrode and the second alignment electrode that are spaced from each other (item 30 between the 21_3 and 22_3). Thus, it would have been obvious to one of ordinary skill art at the time of filing in the art to include the right and left patterns 21 and 22 to ensure alignment of the device during fabrication improving display quality. As to the recitation of and wherein the pad electrode is located at a layer different from the first and second alignment electrodes. Choung teaches the bad at the same level as the circuit layer figure 5 item WPD is the same level as 140s and SEL and DEL. Kim teaches two embodiments figure 21 where the alignment electrodes items 21 and 22 are above the lamination of WPD of the pad. Kim also teaches figure 23 the pad electrode PAD_C is at a different lamination level due to WPD than the alignment electrodes. Further Kim would suggest putting the alignment electrodes above the circuit layer S1 and D1 corresponding to SEL and DEL of Choung. Choung teaches that the pad is at the same level as SEL and DEL, corresponding to S1 and D1. Thus, Choung in view of Kim teach and suggest the pad electrode is located at a layer different from the first and second alignment electrodes. b. As to claim 2, Choung and Kim would suggest further comprising a passivation layer between the circuit element layer and the alignment electrode layer, wherein the passivation layer includes a second opening exposing the pad electrode (item 164 or item 165 of Choung exposes the pad at PDOP). c. As to claim 3 Choung teaches wherein the passivation layer comprises an overlapping part on an upper surface of the pad electrode OP2 and forming the second opening (see attached diagram) , and wherein the pad upper electrode covers a portion of the upper surface of the pad electrode exposed by the second opening beyond the overlapping part (due to the sloped nature145 extends beyond op2 slight covering a portion of the pad exposed due to opening 2). PNG media_image1.png 436 757 media_image1.png Greyscale d. As to claim 4, Choung teaches due to the sloped nature of item 145 and OP2 wherein a width of the first opening is smaller than a width of the second opening. e. As to claim 8, Choung teaches wherein the passivation layer comprises an overlapping part on an upper surface of the pad electrode (OP2) and forming the second opening (see attached figure), and wherein the pad upper electrode covers a portion of an upper surface of the overlapping part (due to the sloped nature 145 extends past OP2 and covers a portion of the pad left exposed from the OP2). PNG media_image1.png 436 757 media_image1.png Greyscale f. As to claim 9, Choung teaches due to the sloped nature of item 145 and OP2 wherein a width of the first opening is smaller than a width of the second opening. g. As to claims 11-12, Kim teaches further comprising a first insulating layer on the alignment electrode layer, wherein the first insulating layer comprises a third opening exposing the pad electrode. PAS1 exposes the pad to allow PAD_C to be formed or to allow external connection. Kim also teaches further comprising an external bank on the first insulating layer and defining an emission area in which the light emitting element is located (BNL2). Thus, it would have been obvious to provide further comprising a first insulating layer on the alignment electrode layer, wherein the first insulating layer comprises a third opening exposing the pad electrode to provide the sufficient passivation to prevent shorting after alignment and fabrication and provide comprising an external bank on the first insulating layer and defining an emission area in which the light emitting element is located, to provide directional output for the light emitter h. As to claim 13, Choung teaches wherein the thin film transistor comprises: a semiconductor layer (item 150); a gate electrode overlapping the semiconductor layer (GEL); and source and drain electrodes electrically connected to the semiconductor layer (CNT2s), and wherein the pad electrode comprises a same material as the source and drain electrodes( CNT2 is the same materials see figure 11 of Choung which deposits the CNT simultaneous with the pad). Response to Arguments Applicant's arguments filed 5/6/2026 have been fully considered but they are not persuasive. Applicant assertion that Kim does not teach the pad electrode is located at a layer different from the first and second alignment electrodes. Is not found convincing. The pad electrode in Kim is item PAD_C due to WPD PAD_C is at a different lamination level. Further as set forth in the rejection. Choung in view of Kim would also teach the pad electrode is located at a layer different from the first and second alignment electrodes since the pad of Choung is at the same level as S1 and D1 in Kim and Kim put the alignment electrodes above this level. Thus, the Choung in view of Kim teaches the limitation of the pad electrode is located at a layer different from the first and second alignment electrodes. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F. Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MATTHEW L. REAMES/ Primary Examiner Art Unit 2896 /MATTHEW L REAMES/Primary Examiner, Art Unit 2896
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Prosecution Timeline

Aug 29, 2023
Application Filed
Feb 06, 2026
Non-Final Rejection mailed — §103, §112
May 06, 2026
Response Filed
May 22, 2026
Final Rejection mailed — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12684892
COMPOUND SEMICONDUCTOR DEVICE
3y 1m to grant Granted Jul 14, 2026
Patent 12684276
ELECTRONIC DEVICE
2y 5m to grant Granted Jul 14, 2026
Patent 12684972
DISPLAY APPARATUS
2y 9m to grant Granted Jul 14, 2026
Patent 12684776
MEMORY DEVICE
2y 9m to grant Granted Jul 14, 2026
Patent 12684962
DISPLAY PANEL, DISPLAY DEVICE, AND METHOD FOR MANUFACTURING DISPLAY DEVICE
2y 9m to grant Granted Jul 14, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
95%
With Interview (+18.0%)
2y 8m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1097 resolved cases by this examiner. Grant probability derived from career allowance rate.

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