Attorney’s Docket Number: 4630.5290000
Filing Date: 08/29/2023
Claimed Foreign Priority Date: none
Applicants: Peng et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Election filed on 02/05/2026.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's elections without traverse of Group Invention I and of Species 3, in the reply filed on 02/05/2026, is acknowledged. Applicant cancelled claims 15-20, added new claims 21-26, and indicated that claims 1-14 and 21-26 read on the elected Group invention and Species. The examiner agrees. Accordingly, pending in this application are claims 1-14 and 21-26.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 5-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US5679606).
Regarding Claim 1, Wang (see, e.g., Fig. 5) shows all aspects of the instant invention, including a structure, comprising:
- a plurality of conductive features (e.g., metal lines 14) disposed on a first layer (e.g., IC structure 10 can be a semiconductor wafer including layers formed in and on the wafer)
- a second layer (e.g., comprising multi-layer stack 20-26 or single layer 26) disposed over the plurality of conductive features and the first layer
wherein the second layer comprises a first triangular-shaped peak corresponding to a first conductive feature, a second triangular-shaped peak corresponding to a second conductive feature, and a valley region between the first and second triangular-shaped peaks, wherein the valley region comprises a height above the first layer that is less than a height of the first and second triangular-shaped peaks above the first layer (see, e.g., Fig. 5).
Regarding Claim 2, Wang (see, e.g., Fig. 5) shows that the first layer comprises a substrate, a conductive layer, a dielectric layer, an interconnect, or combinations thereof (e.g., 10 is a semiconductor wafer, thus a substrate).
Regarding Claim 3, Wang (see, e.g., Fig. 5) shows that each conductive feature in the plurality of conductive features comprises a metal or a mandrel (e.g., metal lines 14 of W or AlCu).
Regarding Claim 5, Wang (see, e.g., Fig. 5) shows that the second layer comprises an etch stop layer, a dielectric layer, a polymer layer, or combinations thereof (e.g., each of 20, 22, 24, and 26 are dielectric layers).
Regarding Claim 6, Wang (see, e.g., Fig. 5) shows that a height of the first and second triangular-shaped peaks above each conductive feature is less than the height of the valley region above the first layer.
Regarding Claim 7, Wang (see, e.g., Fig. 5) shows that the height of the valley region above the first layer is greater than a height of each conductive feature.
Regarding Claim 8, Wang (see, e.g., Fig. 5) shows that a top surface of the valley region in the second layer is substantially flat.
Regarding Claim 9, Wang (see, e.g., Fig. 5) shows that the second layer comprises an angle between the top surface of the valley region and the triangular-shaped peaks ranging from about 90o to about 150°.
Regarding Claim 10, Wang (see, e.g., Fig. 5) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a plurality of conductive features (e.g., metal lines 14) on a first layer (e.g., IC structure 10 can be a semiconductor wafer including layers formed in and on the wafer) having a height above the first layer and a distance between each conductive feature in the plurality of conductive features
- a second layer (e.g., comprising multi-layer stack 20-26 or single layer 26) over the plurality of conductive features and the first layer, the second layer comprising a first height above the conductive features and a second height above the first layer
wherein the second layer comprises a first triangular-shaped peak above a first conductive feature, a second triangular-shaped peak above a second conductive feature, and a valley region between the first and second triangular-shaped peaks, wherein a peak-to- peak distance between the first triangular-shaped peak and the second triangular-shaped peak is greater than the distance between the first conductive feature and the second conductive feature (see, e.g., Fig. 5).
Regarding Claim 11, Wang (see, e.g., Fig. 5) shows that:
- the second layer comprises a valley region disposed above the first layer between the first triangular-shaped peak above the first conductive feature and the second triangular-shaped peak above the second conductive feature
- the second layer comprises a valley region height above the first layer that is greater than the height of each conductive feature in the plurality of conductive features.
Regarding Claim 12, Wang (see, e.g., Fig. 5) shows that each conductive feature in the plurality of conductive features is a metal interconnect, a mandrel, or combinations thereof (e.g., metal lines 14 of W or AlCu), and the second layer comprises an etch stop layer, a dielectric layer, a polymer layer, or combinations thereof (e.g., each of 20, 22, 24, and 26 are dielectric layers).
Regarding Claim 13, Wang (see, e.g., Fig. 5) shows that the second layer comprises a substantially flat valley region.
Claims 1-13, 21-22, and 24-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (US2022/0254697).
Regarding Claim 1, Liu (see, e.g., Fig. 2) shows all aspects of the instant invention, including a structure, comprising:
- a plurality of conductive features (e.g., UTM structures 204) disposed on a first layer (e.g., dielectric layer 202)
- a second layer (e.g., passivation layer 206 or passivation oxide 218) disposed over the plurality of conductive features and the first layer
wherein the second layer comprises a first triangular-shaped peak corresponding to a first conductive feature, a second triangular-shaped peak corresponding to a second conductive feature, and a valley region between the first and second triangular-shaped peaks, wherein the valley region comprises a height above the first layer that is less than a height of the first and second triangular-shaped peaks above the first layer (see, e.g., Fig. 2).
Regarding Claim 2, Liu (see, e.g., Fig. 2) shows that the first layer comprises a substrate, a conductive layer, a dielectric layer, an interconnect, or combinations thereof (e.g., 202 is a dielectric layer).
Regarding Claim 3, Liu (see, e.g., Fig. 2) shows that each conductive feature in the plurality of conductive features comprises a metal or a mandrel (e.g., UTM structures 204 are metal layers).
Regarding Claim 4, Liu (see, e.g., Fig. 2) discloses that a spacing s between adjacent UTM structures 204 may be greater than or equal to approximately 1.8 micrometers. Therefore, Liu shows that a distance between each conductive feature in the plurality of conductive features ranges from about 1 micron to about 5 microns.
Regarding Claim 5, Liu (see, e.g., Fig. 2 and Par. [0014) discloses that passivation layer 206 includes three passivation oxides 208, 214, and 218 of dielectric material. Therefore, Liu shows that the second layer comprises an etch stop layer, a dielectric layer, a polymer layer, or combinations thereof.
Regarding Claim 6, Liu (see, e.g., Fig. 2) shows that a height of the first and second triangular-shaped peaks above each conductive feature is less than the height of the valley region above the first layer.
Regarding Claim 7, Liu (see, e.g., Fig. 2) shows that the height of the valley region above the first layer is greater than a height of each conductive feature.
Regarding Claim 8, Liu (see, e.g., Fig. 2) shows that a top surface of the valley region in the second layer is substantially flat.
Regarding Claim 9, Liu (see, e.g., Fig. 2) shows that the second layer comprises an angle between the top surface of the valley region and the triangular-shaped peaks ranging from about 90o to about 150° (e.g., profile angle θ of at least approximately 110 degrees).
Regarding Claim 10, Liu (see, e.g., Fig. 2) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a plurality of conductive features (e.g., UTM structures 204) on a first layer (e.g., dielectric layer 202) having a height above the first layer and a distance between each conductive feature in the plurality of conductive features
- a second layer (e.g., passivation layer 206 or passivation oxide 218) over the plurality of conductive features and the first layer, the second layer comprising a first height above the conductive features and a second height above the first layer
wherein the second layer comprises a first triangular-shaped peak above a first conductive feature, a second triangular-shaped peak above a second conductive feature, and a valley region between the first and second triangular-shaped peaks, wherein a peak-to- peak distance between the first triangular-shaped peak and the second triangular-shaped peak is greater than the distance between the first conductive feature and the second conductive feature (see, e.g., Fig. 2).
Regarding Claim 11, Liu (see, e.g., Fig. 2) shows that:
- the second layer comprises a valley region disposed above the first layer between the first triangular-shaped peak above the first conductive feature and the second triangular-shaped peak above the second conductive feature
- the second layer comprises a valley region height above the first layer that is greater than the height of each conductive feature in the plurality of conductive features.
Regarding Claim 12, Liu (see, e.g., Fig. 2) shows that each conductive feature in the plurality of conductive features is a metal interconnect, a mandrel, or combinations thereof (e.g., UTM structures 204 are metal layers), and the second layer comprises an etch stop layer, a dielectric layer, a polymer layer, or combinations thereof (e.g., 206 includes three passivation oxides 208, 214, and 218 of dielectric material).
Regarding Claim 13, Liu (see, e.g., Fig. 2) shows that the second layer comprises a substantially flat valley region.
Regarding Claim 21, Liu (see, e.g., Fig. 2) shows all aspects of the instant invention, including a semiconductor structure, comprising:
- first and second conductive features (e.g., UTM structures 204) on a first dielectric layer (e.g., dielectric layer 202)
- a second dielectric layer (e.g., passivation layer 206 or passivation oxide 218 are of dielectric material) on the first dielectric layer and covering the first and second conductive features, wherein the second dielectric layer comprises:
a first triangular-shaped peak covering the first conductive feature
a second triangular-shaped peak covering the second conductive feature
a valley region between the first and second triangular-shaped peaks, wherein a top surface of the valley region is substantially flat.
Regarding Claim 22, Liu (see, e.g., Fig. 2) shows that a top surface of the valley region is above top surfaces of the first and second conductive features.
Regarding Claim 24, Liu (see, e.g., Fig. 2) discloses that a spacing s between adjacent UTM structures 204 may be greater than or equal to approximately 1.8 micrometers. Therefore, Liu shows that a distance between the first and second conductive features ranges from about 1 micron to about 5 microns.
Regarding Claim 25, Liu (see, e.g., Fig. 2) shows that the first and second conductive features comprise a metal interconnect or a mandrel (e.g., UTM structures 204 are metal layers).
Regarding Claim 26, Liu (see, e.g., Fig. 2) shows that the second dielectric layer comprises an angle between a top surface of the valley region and the first triangular-shaped peak ranging from about 90o to about 150° (e.g., profile angle θ of at least approximately 110 degrees).
Claims 1-3, 5-8, 10-14, 21-23, and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. (US2021/0249321).
Regarding Claim 1, Wu (see, e.g., Fig. 10) shows all aspects of the instant invention, including a structure, comprising:
- a plurality of conductive features (e.g., conductive features 145A-C) disposed on a first layer (e.g., device layer 110, metallization layer 115, or metallization layer 116)
- a second layer (e.g., comprising multi-layer stack 155A-D or single layer 155D) disposed over the plurality of conductive features and the first layer
wherein the second layer comprises a first triangular-shaped peak corresponding to a first conductive feature, a second triangular-shaped peak corresponding to a second conductive feature, and a valley region between the first and second triangular-shaped peaks, wherein the valley region comprises a height above the first layer that is less than a height of the first and second triangular-shaped peaks above the first layer (see, e.g., Fig. 10).
Regarding Claim 2, Wu (see, e.g., Fig. 10) shows that the first layer comprises a substrate, a conductive layer, a dielectric layer, an interconnect, or combinations thereof (e.g., 110 comprises a substrate 105, conductive layer 125 or 126, dielectric layer 120, contact 122, or via 130 or 131).
Regarding Claim 3, Wu (see, e.g., Fig. 10) shows that each conductive feature in the plurality of conductive features comprises a metal or a mandrel (e.g., conductive features 145A-C comprise tungsten or aluminum).
Regarding Claim 5, Wu (see, e.g., Fig. 10) discloses that each passivation layers 155A-155C comprises silicon dioxide. Therefore, Wu shows that the second layer comprises an etch stop layer, a dielectric layer, a polymer layer, or combinations thereof.
Regarding Claim 6, Wu (see, e.g., Fig. 10) shows that a height of the first and second triangular-shaped peaks above each conductive feature is less than the height of the valley region above the first layer.
Regarding Claim 7, Wu (see, e.g., Fig. 10) shows that the height of the valley region above the first layer is greater than a height of each conductive feature.
Regarding Claim 8, Wu (see, e.g., Fig. 10) shows that a top surface of the valley region in the second layer is substantially flat.
Regarding Claim 10, Wu (see, e.g., Fig. 10) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a plurality of conductive features (e.g., conductive features 145A-C) on a first layer (e.g., device layer 110, metallization layer 115, or metallization layer 116) having a height above the first layer and a distance between each conductive feature in the plurality of conductive features
- a second layer (e.g., comprising multi-layer stack 155A-D or single layer 155D) over the plurality of conductive features and the first layer, the second layer comprising a first height above the conductive features and a second height above the first layer
wherein the second layer comprises a first triangular-shaped peak above a first conductive feature, a second triangular-shaped peak above a second conductive feature, and a valley region between the first and second triangular-shaped peaks, wherein a peak-to- peak distance between the first triangular-shaped peak and the second triangular-shaped peak is greater than the distance between the first conductive feature and the second conductive feature (see, e.g., Fig. 10).
Regarding Claim 11, Wu (see, e.g., Fig. 10) shows that:
- the second layer comprises a valley region disposed above the first layer between the first triangular-shaped peak above the first conductive feature and the second triangular-shaped peak above the second conductive feature
- the second layer comprises a valley region height above the first layer that is greater than the height of each conductive feature in the plurality of conductive features.
Regarding Claim 12, Wu (see, e.g., Fig. 10) shows that each conductive feature in the plurality of conductive features is a metal interconnect, a mandrel, or combinations thereof (e.g., conductive features 145A-C comprise tungsten or aluminum), and the second layer comprises an etch stop layer, a dielectric layer, a polymer layer, or combinations thereof (e.g., each passivation layers 155A-155C comprises silicon dioxide).
Regarding Claim 13, Wu (see, e.g., Fig. 10) shows that the second layer comprises a substantially flat valley region.
Regarding Claim 14, Wu (see, e.g., Fig. 10) shows an interconnect (e.g., comprising conductive pillar 210 and UBM 205) extending through the second layer and in contact with a top of at least one conductive feature in the plurality of conductive features.
Regarding Claim 21, Wu (see, e.g., Fig. 10) shows all aspects of the instant invention, including a semiconductor structure, comprising:
- first and second conductive features (e.g., two consecutive conductive features of 145A-C) on a first dielectric layer (e.g., dielectric layer 120)
- a second dielectric layer (e.g., comprising silicon dioxide multi-layer stack 155A-D or single layer 155D) on the first dielectric layer and covering the first and second conductive features, wherein the second dielectric layer comprises:
a first triangular-shaped peak covering the first conductive feature
a second triangular-shaped peak covering the second conductive feature
a valley region between the first and second triangular-shaped peaks, wherein a top surface of the valley region is substantially flat.
Regarding Claim 22, Wu (see, e.g., Fig. 10) shows that a top surface of the valley region is above top surfaces of the first and second conductive features.
Regarding Claim 23, Wu (see, e.g., Fig. 10) shows that the second dielectric layer comprises silicon dioxide, silicon nitride, a polymer, or combinations thereof (e.g., each passivation layers 155A-155C comprises silicon dioxide).
Regarding Claim 25, Wu (see, e.g., Fig. 10) shows that the first and second conductive features comprise a metal interconnect or a mandrel (e.g., conductive features 145A-C comprise tungsten or aluminum).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose semiconductor devices having passivation layers with triangular-shaped peaks above conductive features anticipating the instant inventions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul at (571) 270-5514. The examiner can normally be reached on Monday-Friday 9am-6pm EST (Eastern Standard Time), or by e-mail via younes.boulghassoul@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814