Prosecution Insights
Last updated: October 04, 2026
Application No. 18/457,975

SEMICONDUCTOR GAP FILL AND PLANARIZATION

Final Rejection §102§103
Filed
Aug 29, 2023
Examiner
BOULGHASSOUL, YOUNES
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
88%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
467 granted / 529 resolved
+20.3% vs TC avg
Moderate +7% lift
Without
With
+7.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
27 currently pending
Career history
556
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
38.9%
-1.1% vs TC avg
§102
32.8%
-7.2% vs TC avg
§112
23.1%
-16.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 529 resolved cases

Office Action

§102 §103
Attorney’s Docket Number: 4630.5290000 Filing Date: 08/29/2023 Claimed Foreign Priority Date: none Applicants: Peng et al. Examiner: Younes Boulghassoul DETAILED ACTION This Office action responds to the Amendment filed on 05/26/2026. Remarks The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Acknowledgment The Amendment filed on 05/26/2026, responding to the Office action mailed on 02/27/2026, has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this application are claims 1-14 and 21-26. Response to Amendment Applicant’s amendments to the Claims have overcome the claim rejections under 35 U.S.C. 102, as previously formulated in the Non-Final Office action mailed on 02/27/2026. Accordingly, all prior claim rejections are hereby withdrawn. However, applicant’s amendments have raised new issues, and new grounds for rejection are presented below, as necessitated by Applicant’s amendments to the claims. Claim Objections Claims 9 and 22 are objected to because of the following informalities: - Claim 9, L.2: amend to --and the first and second triangular-shaped peaks …--, in accordance with the claim language introduced in claim 1, L. 11-12: “the first and second triangular-shaped peaks”. - Claim 22, L. 1: amend to --wherein [[a]] the top surface of the valley region …--, in accordance with the claim language introduced in claim 21, L. 10: “a top surface of the valley region…”. Appropriate corrections are required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 10-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Annapragada et al. (US6028013). Regarding Claim 10, Annapragada (see, e.g., Fig. 2) shows all aspects of the instant invention, including a structure, comprising: - plurality of conductive features (e.g., metallization lines 112) on a first layer (e.g., substrate 100) having a thickness above the first layer along a direction perpendicular to a top surface of the first layer and a distance between each conductive feature in the plurality of conductive features - a second layer (e.g., FSG oxide layer 120) over the plurality of conductive features and the first layer, the second layer comprising a dielectric material (e.g., FSG oxide) in contact with the plurality of conductive features, wherein: the second layer comprises a first triangular-shaped peak above a first conductive feature (e.g., pyramid 120a above 112a), a second triangular-shaped peak above a second conductive feature (e.g., pyramid 120b above 112b), and a valley region between the first and second triangular-shaped peaks (see, e.g., Fig. 2) the dielectric material has a first thickness along the direction above the plurality of conductive features and a second thickness along the direction above the first layer (see, e.g., Fig. 2) the second thickness of the dielectric material above the first layer is greater than the thickness of the plurality of the conductive features above the first layer (see, e.g., Fig. 2) a sidewall surface of the first triangular-shaped peak abuts a top surface of the valley region (see, e.g., Fig. 2). Regarding Claim 11, Annapragada (see, e.g., Fig. 2) shows that the valley region is disposed above the first layer between the first conductive feature (e.g., 112a) and the second conductive feature (e.g., 112b). Regarding Claim 12, Annapragada (see, e.g., Fig. 2) shows that each conductive feature in the plurality of conductive features is a metal interconnect, a mandrel, or combinations thereof (e.g., metallization lines 112), and the second layer comprises an etch stop layer, a dielectric layer, a polymer layer, or combinations thereof (e.g., FSG oxide/dielectric 120). Regarding Claim 13, Annapragada (see, e.g., Fig. 2) shows that the valley region of the second layer is substantially flat. Claims 1-3, 5-13, 21-23, and 25-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dawson (US6057603). Regarding Claim 1, Dawson (see, e.g., Fig. 1A and Col. 1, L. 53 to Col. 2, L. 6) shows all aspects of the instant invention, including a structure, comprising: - a plurality of conductive features (e.g., patterned metal "stacks" 105) disposed on a first layer (e.g., dielectric layer 102) - a second layer (e.g., gap fill layer 112 of SiO2) comprising a dielectric material disposed over the plurality of conductive features and the first layer, wherein: the second layer comprises a first triangular-shaped peak (e.g., left peak 114) corresponding to a first conductive feature, a second triangular-shaped peak (e.g., middle peak 114) corresponding to a second conductive feature, and a valley region between the first and second triangular-shaped peaks (see, e.g., Fig. 1A) the dielectric material (e.g., 112 of SiO2) is in contact with the plurality of conductive features (see, e.g., Fig. 1A) a thickness of each conductive feature above the first layer along a direction perpendicular to a top surface of the first layer is less than a thickness of the dielectric material along the direction at the first and second triangular-shaped peaks (e.g., 105 is about 1 micron vs. 116 is about 1.2 microns). Regarding Claim 2, Dawson (see, e.g., Fig. 1A) shows that the first layer comprises a substrate, a conductive layer, a dielectric layer, an interconnect, or combinations thereof (e.g., 102 is a dielectric layer of SiO2). Regarding Claim 3, Dawson (see, e.g., Fig. 1A) shows that each conductive feature in the plurality of conductive features comprises a metal or a mandrel (e.g., 105 comprises Ti or Al). Regarding Claim 5, Dawson (see, e.g., Fig. 1A) shows that the second layer comprises an etch stop layer, a dielectric layer, a polymer layer, or combinations thereof (e.g., 112 is a gap fill layer/dielectric of SiO2). Regarding Claim 6, Dawson (see, e.g., Fig. 1A) shows that the thickness of the second layer (e.g., 112) at the first and second triangular-shaped peaks above each conductive feature (e.g., 105) is less than a thickness of the dielectric material (e.g., SiO2 of 112) along the direction at the valley region above the first layer (e.g., 102). Regarding Claim 7, Dawson (see, e.g., Fig. 1A) shows that the thickness of the dielectric material (e.g., SiO2 of 112) at the valley region above the first layer (e.g., 102) is greater than the thickness of each conductive feature (e.g., 105). Regarding Claim 8, Dawson (see, e.g., Fig. 1A) shows that a top surface of the second layer (e.g., 112) at the valley region is substantially flat. Regarding Claim 9, Dawson (see, e.g., Fig. 1A) shows that the second layer (e.g., 112) comprises an angle between the top surface of the valley region and the triangular-shaped peaks ranging from about 90o to about 150°. Regarding Claim 10, Dawson (see, e.g., Fig. 1A and Col. 1, L. 53 to Col. 2, L. 6) shows all aspects of the instant invention, including a structure, comprising: - plurality of conductive features (e.g., patterned metal "stacks" 105) on a first layer (e.g., dielectric layer 102) having a thickness above the first layer along a direction perpendicular to a top surface of the first layer and a distance between each conductive feature in the plurality of conductive features - a second layer (e.g., gap fill layer 112 of SiO2) over the plurality of conductive features and the first layer, the second layer comprising a dielectric material (e.g., SiO2) in contact with the plurality of conductive features, wherein: the second layer comprises a first triangular-shaped peak above a first conductive feature (e.g., left peak 114), a second triangular-shaped peak above a second conductive feature (e.g., middle peak 114), and a valley region between the first and second triangular-shaped peaks (see, e.g., Fig. 1A) the dielectric material has a first thickness along the direction above the plurality of conductive features and a second thickness along the direction above the first layer (see, e.g., Fig. 1A) the second thickness of the dielectric material above the first layer is greater than the thickness of the plurality of the conductive features above the first layer (see, e.g., Fig. 1A: 116 is about 1.2 microns vs. 105 is about 1 micron) a sidewall surface of the first triangular-shaped peak abuts a top surface of the valley region (see, e.g., Fig. 1A). Regarding Claim 11, Dawson (see, e.g., Fig. 1A) shows that the valley region is disposed above the first layer between the first conductive feature (e.g., left 114) and the second conductive feature (e.g., middle 114). Regarding Claim 12, Dawson (see, e.g., Fig. 1A) shows that each conductive feature in the plurality of conductive features is a metal interconnect, a mandrel, or combinations thereof (e.g., metal "stacks" 105), and the second layer comprises an etch stop layer, a dielectric layer, a polymer layer, or combinations thereof (e.g., gap fill layer 112 of SiO2). Regarding Claim 13, Dawson (see, e.g., Fig. 1A) shows that the valley region of the second layer is substantially flat. Regarding Claim 21, Dawson (see, e.g., Fig. 1A and Col. 1, L. 53 to Col. 2, L. 6) shows all aspects of the instant invention, including a structure, comprising: - first and second conductive features on a first dielectric layer (e.g., left and middle patterned metal "stacks" 105 on dielectric layer 102) - a second dielectric layer (e.g., gap fill layer 112 of SiO2) on the first dielectric layer and covering the first and second conductive features, wherein: the second dielectric layer comprises a dielectric material (e.g., 112 of SiO2) in contact with the first and second conductive features the second dielectric layer comprises a first triangular-shaped peak (e.g., left peak 114) covering the first conductive feature, a second triangular-shaped peak (e.g., middle peak 114) covering the second conductive feature, and a valley region between the first and second triangular-shaped peaks (see, e.g., Fig. 1A) a top surface of the valley region is substantially flat (see, e.g., Fig. 1A) a first thickness of the dielectric material along a direction perpendicular to a top surface of the first dielectric layer at the first triangular-shaped peak above the first conductive feature is greater than a second thickness of the first conductive feature along the direction (see, e.g., Fig. 1A: 116 is about 1.2 microns vs. 105 is about 1 micron). Regarding Claim 22, Dawson (see, e.g., Fig. 1A) shows that a top surface of the valley region is above top surfaces of the first and second conductive features. Regarding Claim 23, Dawson (see, e.g., Fig. 1A) shows that the second dielectric layer comprises silicon dioxide, silicon nitride, a polymer, or combinations thereof (e.g., 112 comprises SiO2). Regarding Claim 25, Dawson (see, e.g., Fig. 1A) shows that the first and second conductive features comprise a metal interconnect or a mandrel (e.g., 105 comprises Ti or Al). Regarding Claim 26, Dawson (see, e.g., Fig. 1A) shows that the second dielectric layer (e.g., 112) comprises an angle between a top surface of the valley region and the first triangular-shaped peak ranging from about 90o to about 150°. Claims 1-3, 5-13, 21-23, and 25-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hung et al. (US6566263). Regarding Claim 1, Hung (see, e.g., Fig. 3) shows all aspects of the instant invention, including a structure, comprising: - a plurality of conductive features (e.g., metal lines comprising 14,18,20) disposed on a first layer (e.g., oxide layer 12 of SiO2) - a second layer (e.g., IMD/passivation layer 30 of HDP CVD oxide) comprising a dielectric material disposed over the plurality of conductive features and the first layer, wherein: the second layer comprises a first triangular-shaped peak corresponding to a first conductive feature, a second triangular-shaped peak corresponding to a second conductive feature, and a valley region between the first and second triangular-shaped peaks (see, e.g., Fig. 3) the dielectric material (e.g., 30 of HDP CVD oxide) is in contact with the plurality of conductive features (see, e.g., Fig. 3) a thickness of each conductive feature above the first layer along a direction perpendicular to a top surface of the first layer is less than a thickness of the dielectric material along the direction at the first and second triangular-shaped peaks (see, e.g., Fig. 3) Regarding Claim 2, Hung (see, e.g., Fig. 3) shows that the first layer comprises a substrate, a conductive layer, a dielectric layer, an interconnect, or combinations thereof (e.g., 12 is a dielectric layer of SiO2). Regarding Claim 3, Hung (see, e.g., Fig. 3) shows that each conductive feature in the plurality of conductive features comprises a metal or a mandrel (e.g., 14,18,20 comprise metals of Al or Ti). Regarding Claim 5, Hung (see, e.g., Fig. 3) shows that the second layer comprises an etch stop layer, a dielectric layer, a polymer layer, or combinations thereof (e.g., 30 is a dielectric layer of HDP CVD oxide). Regarding Claim 6, Hung (see, e.g., Fig. 3) shows that the thickness of the second layer (e.g., 30) at the first and second triangular-shaped peaks above each conductive feature (e.g., 14,18,20) is less than a thickness of the dielectric material along the direction at the valley region above the first layer (e.g., 12). Regarding Claim 7, Hung (see, e.g., Fig. 3) shows that the thickness of the dielectric material (e.g., HDP CVD oxide 30) at the valley region above the first layer (e.g., 12) is greater than the thickness of each conductive feature (e.g., 14,18,20). Regarding Claim 8, Hung (see, e.g., Fig. 3) shows that a top surface of the second layer (e.g., 30) at the valley region is substantially flat. Regarding Claim 9, Hung (see, e.g., Fig. 3) shows that the second layer (e.g., 30) comprises an angle between the top surface of the valley region and the triangular-shaped peaks ranging from about 90o to about 150°. Regarding Claim 10, Hung (see, e.g., Fig. 3) shows all aspects of the instant invention, including a structure, comprising: - plurality of conductive features (e.g., metal lines comprising 14,18,20) on a first layer (e.g., oxide layer 12 of SiO2) having a thickness above the first layer along a direction perpendicular to a top surface of the first layer and a distance between each conductive feature in the plurality of conductive features - a second layer (e.g., IMD/passivation layer 30 of HDP CVD oxide) over the plurality of conductive features and the first layer, the second layer comprising a dielectric material (e.g., HDP CVD oxide) in contact with the plurality of conductive features, wherein: the second layer comprises a first triangular-shaped peak above a first conductive feature, a second triangular-shaped peak above a second conductive feature, and a valley region between the first and second triangular-shaped peaks (see, e.g., Fig. 3) the dielectric material has a first thickness along the direction above the plurality of conductive features and a second thickness along the direction above the first layer (see, e.g., Fig. 3) the second thickness of the dielectric material above the first layer is greater than the thickness of the plurality of the conductive features above the first layer (see, e.g., Fig. 3) a sidewall surface of the first triangular-shaped peak abuts a top surface of the valley region (see, e.g., Fig. 3). Regarding Claim 11, Hung (see, e.g., Fig. 3) shows that the valley region is disposed above the first layer between the first conductive feature and the second conductive feature. Regarding Claim 12, Hung (see, e.g., Fig. 3) shows that each conductive feature in the plurality of conductive features is a metal interconnect, a mandrel, or combinations thereof (e.g., metal lines 14,18,20 of Al or Ti), and the second layer comprises an etch stop layer, a dielectric layer, a polymer layer, or combinations thereof (e.g., IMD/passivation 30 of HDP CVD oxide). Regarding Claim 13, Hung (see, e.g., Fig. 3) shows that the valley region of the second layer is substantially flat. Regarding Claim 21, Hung (see, e.g., Fig. 3) shows all aspects of the instant invention, including a structure, comprising: - first and second conductive features on a first dielectric layer (e.g., metal lines comprising 14,18,20) - a second dielectric layer (e.g., IMD/passivation layer 30 of HDP CVD oxide) on the first dielectric layer and covering the first and second conductive features, wherein: the second dielectric layer comprises a dielectric material (e.g., 30 of HDP CVD oxide) in contact with the first and second conductive features the second dielectric layer comprises a first triangular-shaped peak covering the first conductive feature, a second triangular-shaped peak covering the second conductive feature, and a valley region between the first and second triangular-shaped peaks (see, e.g., Fig. 3) a top surface of the valley region is substantially flat (see, e.g., Fig. 3) a first thickness of the dielectric material along a direction perpendicular to a top surface of the first dielectric layer at the first triangular-shaped peak above the first conductive feature is greater than a second thickness of the first conductive feature along the direction (see, e.g., Fig. 3). Regarding Claim 22, Hung (see, e.g., Fig. 3) shows that a top surface of the valley region is above top surfaces of the first and second conductive features. Regarding Claim 23, Hung (see, e.g., Fig. 3) shows that the second dielectric layer comprises silicon dioxide, silicon nitride, a polymer, or combinations thereof (e.g., HDP CVD oxide). Regarding Claim 25, Hung (see, e.g., Fig. 3) shows that the first and second conductive features comprise a metal interconnect or a mandrel (e.g., metal lines 14,18,20 of Al or Ti). Regarding Claim 26, Hung (see, e.g., Fig. 3) shows that the second dielectric layer (e.g., 30) comprises an angle between a top surface of the valley region and the first triangular-shaped peak ranging from about 90o to about 150°. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 4 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US6566263) in view of Liu et al. (US2022/0254697). Regarding Claim 4, Hung is silent about a distance between each conductive feature in the plurality of conductive features ranging from about 1 micron to about 5 microns. Liu (see, e.g., Fig. 2), on the other hand and in the same field of endeavor, teaches an arrangement of UTM structures 204 such that a spacing s between adjacent UTM structures may be greater than or equal to approximately 1.8 micrometers. Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed, to have a distance between each conductive feature in the plurality of conductive features ranging from about 1 micron to about 5 microns in the structure of Hung, because it is known in the semiconductor art that adjacent UTM structures can be arranged with a spacing of at least 1.8 micrometers, as suggested by Liu, and implementing a known conductive feature arrangement for its conventional purpose would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007). Regarding Claim 24, Hung is silent about a distance between the first and second conductive features ranges from about 1 micron to about 5 microns. Also, see comments stated above in Par. 51-52 with regards to Claim 4, which are considered repeated here. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US6566263) in view of Chen et al. (US2021/0217659). Regarding Claim 4, Hung is silent about an interconnect extending through the second layer and in contact with a top of at least one conductive feature in the plurality of conductive features. Chen (see, e.g., Figs. 7-13), on the other hand and in the same field of endeavor, teaches UTM lines 36 covered by a passivation structure 50 and having triangular-shaped peaks corresponding to the underlying UTM lines, wherein further processing steps can be performed to define conductive pillar bumps 92 extending through passivation structure 50 and in contact with a top of at least one UTM lines 36, so as to enable electrical connectivity to said UTM lines. Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed, to have an interconnect extending through the second layer and in contact with a top of at least one conductive feature in the plurality of conductive features in the structure of Hung, because it is known in the semiconductor art that conductive pillar bumps can be implemented to extend through a passivation structure and to contact with a top of at least one underlying UTM line, so as to enable electrical connectivity to said UTM lines, as suggested by Chen, and implementing a known interconnect arrangement for its conventional purpose would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007). Response to Arguments Applicant’s remarks with respect to the claims filed on 05/26/2026 have been considered but are moot in view of the new grounds of rejection. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul whose telephone number is (571) 270-5514. The examiner can normally be reached Monday-Friday 9am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814
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Prosecution Timeline

Aug 29, 2023
Application Filed
Feb 27, 2026
Non-Final Rejection mailed — §102, §103
Apr 14, 2026
Interview Requested
Apr 23, 2026
Applicant Interview (Telephonic)
Apr 23, 2026
Examiner Interview Summary
May 26, 2026
Response Filed
Aug 26, 2026
Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
88%
Grant Probability
95%
With Interview (+7.0%)
2y 2m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 529 resolved cases by this examiner. Grant probability derived from career allowance rate.

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