Prosecution Insights
Last updated: July 17, 2026
Application No. 18/458,630

3D COMB NANOSHEET AND PI/2 ROTATED NANOSHEET

Non-Final OA §102§103
Filed
Aug 30, 2023
Examiner
SALAZ, SAMMANTHA KATELYN
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Tokyo Electron Limited
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
22 granted / 25 resolved
+20.0% vs TC avg
Strong +18% interview lift
Without
With
+17.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
20 currently pending
Career history
54
Total Applications
across all art units

Statute-Specific Performance

§103
82.5%
+42.5% vs TC avg
§102
5.8%
-34.2% vs TC avg
§112
7.3%
-32.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 25 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 1-8 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Invention I, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 2/18/2026. Examiner’s note: Examiner erroneously excluded claims 16-20 in invention II in the election/restriction requirement of 12/29/2025, as Applicant pointed out in their traversal. After taking the election of Species D into consideration, the elected claims would have been claims 9-19, as claim 20 is directed towards Species C. However, as independent claim 16 is indicated as allowable, claim 20 would be rejoined, rendering the election of species moot. The election requirement between invention I and invention II is still upheld. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lilak et al. (US 2020/0098756 A1, hereafter Lilak). Regarding claim 9, Lilak teaches a method of manufacturing a semiconductor device, the method comprising: forming channel structures (132, Fig. 12, [0036]) over a substrate (110, Fig. 11, [0035]), wherein the channel structures (132) are stacked over each other along a first direction (Z-direction, Fig. 11) substantially perpendicular to a working surface of the substrate (110) and each configured to have a current direction along a second direction (Y-direction, Fig. 11) substantially parallel to the working surface of the substrate (110), and the channel structures (132) each have a shape of a nanosheet (132 described as nanosheet in [0037]) extending substantially perpendicular to the working surface of the substrate (110) (the nanosheets have a thickness, meaning they extend in the Z-direction); forming source/drain (S/D) structures (120, Fig. 11, [0036]) on opposing sides of the channel structure (132) along the second direction (Y-direction); and forming gate structures (144, Fig. 11, [0037]) on opposite sides of the channel structures (132) along a third direction (X-direction, Fig. 11) substantially parallel to the working surface of the substrate (110). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lilak as applied to claim 9 above, and further in view of Chang et al. (US 2023/0209836 A1, hereafter Chang). Regarding claim 10, Lilak teaches the method of claim 9. Lilak further teaches forming a layer stack (134, Fig. 7, [0060]) over the substrate (110, Fig. 11, [0035]), the layer stack (134) including sacrificial layers (136, Fig. 7, [0063]); and directionally etching (described in [0064]-[0066] and shown with final channels 132 in Fig. 12) the sacrificial layers (136) to form individual nanosheets (132, Fig. 12, [0036]) that are spaced apart from one another in the third direction (X-direction, Fig. 11) and extend substantially perpendicular to the working surface of the substrate (the nanosheets have a thickness, meaning they extend in the Z-direction). Lilak fails to teach forming a layer stack over the substrate, the layer stack including dielectric layers and sacrificial layers alternatingly stacked over each other. However, Chang teaches in Fig. 13 the formation of a FET similar to Lilak in which the layer stack (49, [0059]) is formed with alternating dielectric layers (41, [0059]) and sacrificial layers (1303, [0059]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the stack formation taught by Lilak to be formed with dielectric layers and sacrificial layers as taught by Chang in order to form dielectric layers that stay intact after an etching step ([0061] of Chang) at a set desired thickness necessary for design constraints ([0039] of Chang). Allowable Subject Matter Claims 11-15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is reasons for the indication of allowable subject matter: Claims 11-14 are objected to primarily because the prior art of record cannot anticipate or render obvious the following limitations, in combination as recited in dependent claim(s) 11: “forming an epitaxial seed structure extending through the layer stack from the substrate; removing the individual nanosheets to uncover side portions of the epitaxial seed structure; and epitaxially growing semiconductor material from the side portions of the epitaxial seed structure to form the channel structures”. The closest prior art of record, Lilak in view of Chang teaches forming gate structures on opposite sides of the channel structures along a first direction substantially parallel to the working surface of the substrate but fails to teach forming an epitaxial seed structure extending through the layer stack from the substrate; removing the individual nanosheets to uncover side portions of the epitaxial seed structure; and epitaxially growing semiconductor material from the side portions of the epitaxial seed structure to form the channel structures, nor could Examiner find any reason for this limitation. Claim 15 is objected to primarily because the prior art of record cannot anticipate or render obvious the following limitations, in combination as recited in dependent claim(s) 15: “forming a first epitaxial seed structure and a second epitaxial seed structure both extending through the layer stack from the substrate; forming an opening in the layer stack between the first epitaxial seed structure and the second epitaxial seed structure, the opening dividing the individual nanosheets into first nanosheets and second nanosheets; replacing the first nanosheets with a first semiconductor material connected to the first epitaxial seed structure; and replacing the second nanosheets with a second semiconductor material connected to the second epitaxial seed structure”. The closest prior art of record, Lilak in view of Chang teaches forming gate structures on opposite sides of the channel structures along a first direction substantially parallel to the working surface of the substrate but fails to teach forming a first epitaxial seed structure and a second epitaxial seed structure both extending through the layer stack from the substrate; forming an opening in the layer stack between the first epitaxial seed structure and the second epitaxial seed structure, the opening dividing the individual nanosheets into first nanosheets and second nanosheets; replacing the first nanosheets with a first semiconductor material connected to the first epitaxial seed structure; and replacing the second nanosheets with a second semiconductor material connected to the second epitaxial seed structure, nor could Examiner find any reason for this limitation. Claim(s) 16 is/are allowed. Claims 16-20 are allowed primarily because the prior art of record cannot anticipate or render obvious the following limitations, in combination as recited in independent claim(s) 16: “forming an epitaxial seed structure that has a shape of comb handle extending through the layer stack from the substrate; removing the sacrificial layers to uncover side portions of the epitaxial seed structure; and epitaxially growing semiconductor material from the side portions of the epitaxial seed structure to form a comb-shaped epitaxial structure”. The closest prior art of record, Lilak in view of Chang teaches forming a semiconductor device with a stack over a substrate but fails to teach “forming an epitaxial seed structure that has a shape of comb handle extending through the layer stack from the substrate; removing the sacrificial layers to uncover side portions of the epitaxial seed structure; and epitaxially growing semiconductor material from the side portions of the epitaxial seed structure to form a comb-shaped epitaxial structure”, nor could Examiner find any reason for this limitation. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SAMMANTHA K SALAZ/Examiner, Art Unit 2892 /LEX H MALSAWMA/Primary Examiner, Art Unit 2892
Read full office action

Prosecution Timeline

Aug 30, 2023
Application Filed
Jun 12, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+17.6%)
3y 2m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 25 resolved cases by this examiner. Grant probability derived from career allowance rate.

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