Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant's election with traverse of Group I, claims 1-8 drawn to device claims is acknowledged. The traversal is on the ground(s) that the subject matter of all claims 1-16 is sufficiently related that a thorough search for the subject matter of any one group of the claims would encompass a search for the subject matter of the remaining claims. This is not found persuasive because claims 9-16 would require further search and for the reason of the last Office Action. The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
The information disclosure statements filed 8/30/23; 11/8/23 have been considered.
Oath/Declaration
Oath/Declaration filed on 8/30/23 has been considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kao et al. (U.S. Patent Publication No. 2020/0381512) in view of LIN (U.S. Patent Publication No. 2015/0021771).
Referring to figures 1-20, Kao et al. teaches semiconductor device, comprising:
a substrate (108);
a source region and a drain region (128/130) disposed in the substrate; a shallow trench isolation (STI) region (140) disposed in the substrate and surrounding the source region and the drain region; a through substrate via (TSV) (104) through the substrate, wherein the through substrate via are adjacent to the shallow trench isolation region, and the through substrate via have a first stress type (see paragraph# 24); and
a compound semiconductor structure (102) isolating the shallow trench isolation region from the through substrate via, wherein the compound semiconductor structure has a second stress type different from the first stress type (see paragraphs# 21-22, it is noted that different material has different stress type).
However, the reference does not clearly teach the plurality of through substrate vias.
LIN teaches a semiconductor device having the plurality of through substrate vias (400, see paragraph# 27, meeting claims 1, 4).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would from the plurality of through substrate vias because it is known in the semiconductor art to provide a more reliable device
Regarding to claim 2, the shallow trench isolation region (140) defines a device area (see figures 1+).
Regarding to claim 3, the plurality of through substrate vias (400) are located in a peripheral area outside the device area (see figure 1 of LIN).
Regarding to claim 4, the compound semiconductor structure (102) is disposed in the substrate (108) and surrounds the through substrate via (104, see figure 1).
Regarding to 5, the shallow trench isolation region (140), the source region, the drain region (128/130), and the compound semiconductor structure (102) extend into the substrate from a frontside surface of the substrate (108, see figure 1).
Regarding to claim 6, a gate structure (124/126) disposed on the frontside surface of the substrate (108) and laterally between the source region and the drain region (128/130, see figure 1a)
Claims 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kao et al. (U.S. Patent Publication No. 2020/0381512) in view of LIN (U.S. Patent Publication No. 2015/0021771), as applied to claims 1-6 above and further in view of Lin et al. (U.S. Patent Publication No. 2015/0061147).
Referring to figures 1-20, Kao et al. teaches semiconductor device, comprising:
a substrate (108);
a source region and a drain region (128/130) disposed in the substrate; a shallow trench isolation (STI) region (140) disposed in the substrate and surrounding the source region and the drain region; a through substrate via (TSV) (104) through the substrate, wherein the through substrate via are adjacent to the shallow trench isolation region, and the through substrate via have a first stress type (see paragraph# 24); and
a compound semiconductor structure (102) isolating the shallow trench isolation region from the through substrate via, wherein the compound semiconductor structure has a second stress type different from the first stress type (see paragraphs# 21-22, it is noted that different material has different stress type).
However, the reference does not clearly teach an interlayer dielectric (ILD) layer located on the frontside surface of the substrate and surrounding the gate structure; a first etch stop layer (ESL) disposed on the interlayer dielectric layer; a first inter-metal dielectric (IMD) layer disposed on the first etch stop layer; a second etch stop layer disposed on the first inter-metal dielectric layer; and a second inter-metal dielectric layer disposed on the second etch stop layer (in claim 7), a source contact plug and a drain contact plug disposed through the interlayer dielectric layer, and respectively connected to the source region and the drain region; a source contact via, a drain contact via, and a gate contact via disposed through the first inter-metal dielectric layer and the first etch stop layer, and respectively connected to the source contact plug, the drain contact plug, and the gate structure; a source metal via, a drain metal via, and a gate metal via disposed through the second inter-metal dielectric layer and the second etch stop layer, and respectively connected to the source contact via, the drain contact via, and the gate contact via; and a source metal layer, a drain metal layer, and a gate metal layer located in the second inter-metal dielectric layer, and respectively coupled to the source metal via, the drain metal via, and the gate metal via (in claim 8).
Lin et al. teaches an interlayer dielectric (ILD) layer (22) located on the frontside surface of the substrate and surrounding the gate structure (see figure 11); a first etch stop layer (ESL) (38) disposed on the interlayer dielectric layer; a first inter-metal dielectric (IMD) layer (40) disposed on the first etch stop layer; a second etch stop layer (44) disposed on the first inter-metal dielectric layer; and a second inter-metal dielectric layer (46) disposed on the second etch stop layer (see figure 11, meeting claim 7), a source contact plug and a drain contact plug (24) disposed through the interlayer dielectric layer (22), and respectively connected to the source region and the drain region; a source contact via, a drain contact via, and a gate contact via (42a/42b) disposed through the first inter-metal dielectric layer and the first etch stop layer, and respectively connected to the source contact plug, the drain contact plug, and the gate structure (see figure 11); a source metal via, a drain metal via, and a gate metal via (48) disposed through the second inter-metal dielectric layer and the second etch stop layer, and respectively connected to the source contact via, the drain contact via, and the gate contact via; and a source metal layer, a drain metal layer, and a gate metal layer (50) located in the second inter-metal dielectric layer, and respectively coupled to the source metal via, the drain metal via, and the gate metal via (see figure 11, meeting claim 8).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would from the plurality of ILD layers, etch stop layers and contact plug, contact via, metal via, metal layer in Kao et al. as taught by Lin et al. because it is known in the semiconductor art to provide higher performance and reliable device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893
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