Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Arguments
Applicant’s arguments, filed 4/30/26, with respect to the rejection(s) of claim(s) 1-8 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of LIN. Newly amended claims 9-16 are directed to method claims. Therefore, claims 9-16 are still withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kao et al. (U.S. Patent Publication No. 2020/0381512) in view of LIN (U.S. Patent Publication No. 2015/0021785).
Referring to figures 1-20, Kao et al. teaches semiconductor device, comprising:
a substrate (108);
a source region and a drain region (128/130) disposed in the substrate; a shallow trench isolation (STI) region (140) disposed in the substrate and surrounding the source region and the drain region; a through substrate via (TSV) (104) through the substrate, wherein the through substrate via are adjacent to the shallow trench isolation region, and the through substrate via have a first stress type (see paragraph# 24); and
a compound semiconductor structure (102) isolating the shallow trench isolation region from the through substrate via, wherein the compound semiconductor structure has a second stress type different from the first stress type (see paragraphs# 21-22, it is noted that different material has different stress type).
However, the reference does not clearly teach the plurality of through substrate vias.
LIN teaches a semiconductor device having the plurality of through substrate vias (400/600, see paragraph# 17, see figures 2a-2d), wherein a bottom surface of the plurality of through substrate vias is coplanar with a backside surface of the substrate (see figure 2C).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would from the plurality of through substrate vias in Kao et al. as taught by LIN because it is known in the semiconductor art to provide a more reliable device
Regarding to claim 2, the shallow trench isolation region (140) defines a device area (see figures 1+).
Regarding to claim 3, the plurality of through substrate vias (400/600) are located in a peripheral area outside the device area (see figure 2a-2d of LIN).
Regarding to claim 4, the compound semiconductor structure (102) is disposed in the substrate (108) and surrounds the through substrate via (104, see figure 1).
Regarding to 5, the shallow trench isolation region (140), the source region, the drain region (128/130), and the compound semiconductor structure (102) extend into the substrate from a frontside surface of the substrate (108, see figure 1).
Regarding to claim 6, a gate structure (124/126) disposed on the frontside surface of the substrate (108) and laterally between the source region and the drain region (128/130, see figure 1a)
Claims 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kao et al. (U.S. Patent Publication No. 2020/0381512) in view of LIN (U.S. Patent Publication No. 2015/0021785), as applied to claims 1-6 above and further in view of Lin et al. (U.S. Patent Publication No. 2015/0061147).
Referring to figures 1-20, Kao et al. teaches semiconductor device, comprising:
a substrate (108);
a source region and a drain region (128/130) disposed in the substrate; a shallow trench isolation (STI) region (140) disposed in the substrate and surrounding the source region and the drain region; a through substrate via (TSV) (104) through the substrate, wherein the through substrate via are adjacent to the shallow trench isolation region, and the through substrate via have a first stress type (see paragraph# 24); and
a compound semiconductor structure (102) isolating the shallow trench isolation region from the through substrate via, wherein the compound semiconductor structure has a second stress type different from the first stress type (see paragraphs# 21-22, it is noted that different material has different stress type).
However, the reference does not clearly teach an interlayer dielectric (ILD) layer located on the frontside surface of the substrate and surrounding the gate structure; a first etch stop layer (ESL) disposed on the interlayer dielectric layer; a first inter-metal dielectric (IMD) layer disposed on the first etch stop layer; a second etch stop layer disposed on the first inter-metal dielectric layer; and a second inter-metal dielectric layer disposed on the second etch stop layer (in claim 7), a source contact plug and a drain contact plug disposed through the interlayer dielectric layer, and respectively connected to the source region and the drain region; a source contact via, a drain contact via, and a gate contact via disposed through the first inter-metal dielectric layer and the first etch stop layer, and respectively connected to the source contact plug, the drain contact plug, and the gate structure; a source metal via, a drain metal via, and a gate metal via disposed through the second inter-metal dielectric layer and the second etch stop layer, and respectively connected to the source contact via, the drain contact via, and the gate contact via; and a source metal layer, a drain metal layer, and a gate metal layer located in the second inter-metal dielectric layer, and respectively coupled to the source metal via, the drain metal via, and the gate metal via (in claim 8).
Lin et al. teaches an interlayer dielectric (ILD) layer (22) located on the frontside surface of the substrate and surrounding the gate structure (see figure 11); a first etch stop layer (ESL) (38) disposed on the interlayer dielectric layer; a first inter-metal dielectric (IMD) layer (40) disposed on the first etch stop layer; a second etch stop layer (44) disposed on the first inter-metal dielectric layer; and a second inter-metal dielectric layer (46) disposed on the second etch stop layer (see figure 11, meeting claim 7), a source contact plug and a drain contact plug (24) disposed through the interlayer dielectric layer (22), and respectively connected to the source region and the drain region; a source contact via, a drain contact via, and a gate contact via (42a/42b) disposed through the first inter-metal dielectric layer and the first etch stop layer, and respectively connected to the source contact plug, the drain contact plug, and the gate structure (see figure 11); a source metal via, a drain metal via, and a gate metal via (48) disposed through the second inter-metal dielectric layer and the second etch stop layer, and respectively connected to the source contact via, the drain contact via, and the gate contact via; and a source metal layer, a drain metal layer, and a gate metal layer (50) located in the second inter-metal dielectric layer, and respectively coupled to the source metal via, the drain metal via, and the gate metal via (see figure 11, meeting claim 8).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would from the plurality of ILD layers, etch stop layers and contact plug, contact via, metal via, metal layer in Kao et al. as taught by Lin et al. because it is known in the semiconductor art to provide higher performance and reliable device.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/ Primary Examiner, Art Unit 2893
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