Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This office action is in response application 18/458927 filed on 08/30/23.
Information Disclosure Statement
The information disclosure statement (IDS) submitted filed before the mailing of a first Office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97(b) (3). Accordingly, the information disclosure statement is being considered by the examiner.
Summary of claims
Claims 1-20 are pending.
Claims 1-20 are rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Berry et al. (US Pub. 2009/0210840).
As to claims 1 the prior art teaches a method, comprising:
for a circuit design, determining a plurality of delay ranges for respective clock pins of a local clock net (see fig 1 paragraph 0016-0019);
wherein each delay range of the plurality of delay ranges includes an upper bound delay and a lower bound delay (see fig 1-2 paragraph 0017-0022);
allocating the upper bound delays of the plurality of delay ranges as setup constraints for the respective clock pins of the local clock net (see fig 1-3 paragraph 0021-0027);
allocating the lower bound delays of the plurality of delay ranges as hold constraints for the respective clock pins of the local clock net (see fig 1-3 paragraph 0027-0032);
and routing the local clock net using the setup constraints and the hold constraints (see fig 1-3 paragraph 0031-0034 and 0040-0044).
As to claim 2, 10 and 18 the prior art teaches wherein the determining the plurality of delay ranges comprises:
creating a linear programming formulation of a delay budget problem for the circuit design, wherein the linear programming formulation includes variables and expressions defining relationships between the variables, and wherein a selected expression maximizes the delay range for each clock pin of the local clock net (see fig 1 paragraph 0017-0018);
and solving the linear programming formulation using a linear programming solver (see fig 1 paragraph 0017-0021).
As to claim 3 and 11 the prior art teaches further comprising: computing the lower bound delays of the plurality of delay ranges for the respective clock pins of the local clock net using scaling factors for the upper bound delays (see fig 1-4 paragraph 0037-0043).
As to claim 4 and 12 the prior art teaches wherein the plurality of delay ranges are determined for a set of one or more skew values (see fig 1-2 paragraph 0016-0017).
As to claims 5, 13 and 19 the prior art teaches further comprising:
performing a plurality of iterations of the determining the plurality of delay ranges for the respective clock pins of the local clock net, wherein each iteration of the plurality of iterations is for a different set of one or more skews (see fig 2-4 paragraph 0025-0030);
wherein the allocating the upper bound delays, the allocating the lower bound delays, and the routing are performed for a selected plurality of delay ranges from a selected iteration of the plurality of iterations (see fig 2-4 paragraph 0028-0032).
As to claim 6 and 14 the prior art teaches wherein the sets of one or more skews for the plurality of iterations are determined based on a binary search technique (see fig 2-5 paragraph 0034-0038).
As to claim 7, 15 and 20 the prior art teaches further comprising:
clustering the clock pins of the local clock net using a proximity-based clustering technique to generate a plurality of clusters (see fig 3-5 paragraph 0023-0026);
and for each cluster, driving each clock pin of the cluster using a same buffer (see fig 3-5 paragraph 0025-0029).
As to claim 8 and 16, the prior art teaches further comprising:
for a selected cluster of the plurality of clusters having a plurality of sub-clusters therein, implementing a spiral search from a centroid of the plurality of sub-clusters for an unused buffer (see fig 3-5 paragraph 0030-0035);
routing a driver of the local clock net to the unused buffer (see fig 3-5 paragraph 0034-0039);
and routing the unused buffer of the local clock net to the buffer of each cluster (see fig 3-5 paragraph 0043-0046).
As to claim 9 the prior art teaches a system, comprising: one or more hardware processors configured to initiate operations including:
for a circuit design, determining a plurality of delay ranges for respective clock pins of a local clock net (see fig 1 paragraph 0016-0019);
wherein each delay range of the plurality of delay ranges includes an upper bound delay and a lower bound delay (see fig 1-2 paragraph 0017-0022);
allocating the upper bound delays of the plurality of delay ranges as setup constraints for the respective clock pins of the local clock net (see fig 1-3 paragraph 0021-0027);
allocating the lower bound delays of the plurality of delay ranges as hold constraints for the respective clock pins of the local clock net (see fig 1-3 paragraph 0027-0032);
and routing the local clock net using the setup constraints and the hold constraints (see fig 1-3 paragraph 0031-0034 and 0040-0044).
As to claim 17 the prior art teaches a computer program product comprising one or more computer readable storage mediums having program instructions embodied therewith, wherein the program instructions are executable by computer hardware to cause the computer hardware to initiate executable operations comprising:
for a circuit design, determining a plurality of delay ranges for respective clock pins of a local clock net (see fig 1 paragraph 0016-0019);
wherein each delay range of the plurality of delay ranges includes an upper bound delay and a lower bound delay (see fig 1-2 paragraph 0017-0022);
allocating the upper bound delays of the plurality of delay ranges as setup constraints for the respective clock pins of the local clock net (see fig 1-3 paragraph 0021-0027);
allocating the lower bound delays of the plurality of delay ranges as hold constraints for the respective clock pins of the local clock net (see fig 1-3 paragraph 0027-0032);
and routing the local clock net using the setup constraints and the hold constraints (see fig 1-3 paragraph 0031-0034 and 0040-0044).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH C TAT whose telephone number is 571 272-1908. The examiner can normally be reached on flex 7:00Am-8PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/BINH C TAT/Primary Examiner, Art Unit 2851
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