DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Election/Restrictions 3
III. Claim Rejections - 35 USC § 112 4
A. Claims 6 and 7 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. 4
IV. Claim Rejections - 35 USC § 103 4
A. Claims 1-4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over US 2026/0052956 (“Ha”). 5
V. Allowable Subject Matter 10
VI. Pertinent Prior Art 13
Conclusion 13
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Election/Restrictions
Applicant’s (1) election without traverse of invention group I and the species D of semiconductor package assembly, (2) the cancellation of claims 8-15, (3) the amendment of previously-presented new claim 21 in the reply filed on 06/02/2026 is acknowledged. Applicant completed the required election of species E of stress modulating device during a telephone interview on 06/17/2026 (Interview Summary attached with this Office action).
Applicant traversed the restriction requirement between invention group I drawn to the stress modulating device and group II drawn to the semiconductor package assembly. However, the amendment to claim 21 to include the common limitation omitting conductive materials from the stress modulating device renders the restriction requirement between invention groups I and II moot, which is hereby withdrawn.
Once the restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 1211, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01. Here, the restriction requirement as to invention groups I and II is withdrawn. However, currently, the restriction requirement among each of the species of stress modulating device and the species of semiconductor package assembly stand.
Applicant also traversed the requirement for restriction among the species of semiconductor package assemblies. However, Applicant failed to provide any reasons for the traversal of the species, arguing instead, only as to the restriction between invention groups I and II, which do not reasonably apply to the species groups. As such, the requirement for restriction among the species groups is still deemed proper and is therefore made FINAL.
The claims drawn to the non-elected species may be entitled to rejoinder under the conditions explained in the Requirement for Election/Restriction.
III. Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
A. Claims 6 and 7 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Each of claims 6 and 7 recites the limitation “N-1 alternating layers”. The claims are indefinite because variable, “N”, is not defined.
For the purposes of examination, the claim will be interpreted as broadly as allowed by the explicit language.
IV. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1-4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over US 2026/0052956 (“Ha”).
Ha states “FIG. 8 shows an example cross section of a wafer 802 after undergoing the example process in FIG. 7.” (Ha: ¶ 92, 1st sentence) With regard to claim 1, Ha discloses, generally in, e.g., Figs. 7 and 8,
1. (Original) A stress modulating device [¶ 60] comprising:
[1] a semiconductor substrate 803 [¶ 92];
[2] a first insulating layer [e.g. first silicon oxide sublayer of 804 (see explanation below)] over a first side [e.g. top side in Fig. 8] of the semiconductor substrate 803 [¶ 92];
[3] a second insulating layer [e.g. first silicon nitride sublayer of 804 (see explanation below)] over the first insulating layer [¶ 92];
[4] a third insulating layer [e.g. first silicon oxide sublayer of 806 (see explanation below)] over a second side of the semiconductor substrate 803 [¶ 92];
[5] a fourth insulating layer [e.g. first silicon nitride sublayer of 806 (see explanation below)] over the third insulating layer [¶ 92]; and
[6] a fifth insulating layer [any one or more of 808, 816, 818] over the fourth insulating layer [¶ 92],
[7] wherein the stress modulating device is substantially free of conductive materials [because the structure is composed of only the single crystal silicon wafer 803 and the insulating layers 804, 806, 808, 816, 818 deposited thereon].
With regard to features [2] and [3] of claim 1, the layer 804, which is made by the process step 710 shown in Fig. 7 (Ha: ¶ 92), can be multilayered and have an overall internal stress that is either tensile or compressive and causes the wafer 804 to bow. In this regard, Ha states,
[0082] FIG. 7 shows a second example process using multiple backside layers to prevent cracking of layers and/or other bow-related issues during a thermal cycle. FIG. 7 starts with depositing one or more frontside layers with a first type of internal stress (tensile or compressive) on a wafer in operation 710. The internal stress from the frontside layer causes the wafer to bow. …
(Ha: ¶ 82; emphasis added)
Ha also explains a multilayered stack of alternating silicon oxide and silicon nitride causes bowing and is typically 32 to 72 layers but can be more than 100 or more than 500 or more than 1000, stating in this regard,
[0043] Bowing is especially likely to occur where large stacks of materials are deposited, for example, in the context of 3D-NAND devices. …
[0044] One example stack that may cause these problems [i.e. bowing] is a stack having alternating layers of oxide and nitride (e.g., silicon oxide/silicon nitride/silicon oxide/silicon nitride, etc.). …
[0046] The frontside stacks may be deposited to any number of layers and thicknesses. In a typical example, the stack includes between about 32-72 layers, and has a total thickness of about 2 μm to about 4 μm. The stress induced in the wafer by the stack may be about −500 MPa to about +500 MPa, resulting in a bow that is frequently about 200 μm to about 400 μm (for a 300 mm wafer), and even greater in some cases. However, modern IC fabrication techniques may produce substrates having frontside layers with much higher internal stresses compared to previous nodes. The frontside may have larger stacks, for example, stacks may be upwards of a 1000 layers. In another example, reduced etch selectivity has led to thicker masks. These stacks may have a thickness of about 4 μm to 12 μm.
[0068] As mentioned, wafer bow may be caused by frontside processing. In some embodiments, frontside processing may deposit a material or stacks of materials with an internal stress, either compressive stress or tensile stress. The stacks of material may be multiple-layer stacks. In some embodiments, multiple-layer stacks may have about 100 or more layers. In some embodiments, multiple-layer stacks may have about 500 or more layers. In some embodiments, the multiple-layer stacks may have about 1000 or more layers. The internal stress of the deposited material or stacks of material may have a magnitude from 0 MPa to about 500 MPa. The stress may be a tensile stress or a compressive stress. The stress may cause significant wafer bowing. … One example stack that may cause these problems is a stack having alternating layers of oxide and nitride (e.g., silicon oxide/silicon nitride/silicon oxide/silicon nitride, etc.).
(Ha: ¶¶ 43, 44, 46, 68; emphasis added)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make layer 804 from, e.g. 32 to 72 alternating layers of “(e.g., silicon oxide/silicon nitride/silicon oxide/silicon nitride, etc.)” (id.) because Ha suggests this.
So done, the claimed “first insulating layer” is silicon oxide and the claimed “second insulating layer” is silicon nitride.
With regard to features [4]-[5] of claim 1, the first backside layer 806 is made by the process step 720 in Fig. 7 and includes “one or more backside layers with a first type of internal stress (tensile or compressive) on the semiconductor substrate” (step 720 in Fig. 7). Ha also states that “first backside layer 806 has the first type of internal stress, e.g., the same internal stress as the frontside layer.” (Ha: ¶ 92; emphasis added). As such, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the “one or more backside layers” of 806 (step 720 in Fig. 7) from a multilayered stack “(e.g., silicon oxide/silicon nitride/silicon oxide/silicon nitride, etc.)” in order to give the same internal stress, i.e. “the first type of internal stress” (Ha: ¶ 92) as that of the frontside layer 804, as suggested by Ha.
So done, the claimed “third insulating layer” is silicon oxide, and the claimed “fourth insulating layer” is silicon nitride.
With regard to feature [6] of claim 1, the layer 808 in Ha, i.e. the claimed “fifth insulating layer” is formed by step 730 in Fig. 7 and has the opposite type of internal stress to that of each of 804 and 806 or has neutral internal stress, i.e. “one or more backside layers with a second type of internal stress, which is opposite the first type or neutral” (step 730 in Fig. 7). Ha states:
[0049] Examples of backside films used to counteract bow include the following: amorphous silicon, silicon oxide, silicon nitride, and silicon oxynitride. Current backside films have high internal stress and are able to mitigate the stresses imparted on the wafer from the frontside layers to reduce or eliminate the wafer bow. Generally, backside layers are made of films with high stress.
[0071] To combat wafer bow caused by a frontside layer with an internal tensile force, a tensile film may be used for the backside film. Tensile films may be formed using specific materials and/or processing conditions. Example materials used to make tensile films include silicon nitrides (SiN), silicon oxynitrides, and polymer layers. Tensile films can be deposited using CVD or PECVD techniques.
[0072] To combat wafer bow caused by a frontside layer with an internal compressive force, a compressive film may be used for the backside film. Compressive films may be formed using specific materials and/or processing conditions. Example materials used to make compressive films include silicon oxides (SiOx), silicon nitrides, aluminum oxides, aluminum nitrides, and polysilicon. Compressive films can be deposited using CVD or PECVD techniques.
(Ha: ¶ 49, 71, 72; emphasis added)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the second backside layer 808 from e.g. silicon nitride having the opposite internal stress to that if the first backside layer 806 because Ha suggests this option.
This is all of the limitations of claim 1.
With regard to claims 2-4 and 6, Ha further discloses,
2. (Original) The stress modulating device of claim 1, wherein:
[1] the first insulating layer [e.g. first silicon oxide sublayer of 804 (supra)] and the third insulating layer [e.g. first silicon oxide sublayer of 806 (supra)] have a first composition; and
[2] the second insulating layer [e.g. first silicon nitride sublayer of 804 (supra)] and the fourth insulating layer [e.g. first silicon nitride sublayer of 806 (supra)] have a second composition,
[3] wherein the first composition is different than the second composition.
3. (Original) The stress modulating device of claim 2, wherein: the fifth insulating 808 layer has the second composition [e.g. silicon nitride (supra)].
4. (Original) The stress modulating device of claim 1, wherein:
[1] the first insulating layer [e.g. first silicon oxide sublayer of 804 (supra)] and the third insulating layer [e.g. first silicon oxide sublayer of 806 (supra)] comprise silicon dioxide [supra]; and
[2] the second insulating layer [e.g. first silicon nitride sublayer of 804 (supra)], the fourth insulating layer [e.g. first silicon nitride sublayer of 806 (supra)] and the fifth insulating layer 808 comprise silicon nitride [supra].
6. (Original) The stress modulating device of claim 2, further comprising: a series of N-1 alternating layers of the first composition and the second composition.
As explained above, either of the multilayered stack of alternating layers of silicon oxide and silicon nitride forming each of the frontside layer 804 and the backside layer 806 may be taken as the claimed “series of N-1 alternating layers of the first composition and the second composition”.
V. Allowable Subject Matter
Pending overcoming the rejection of claim 7 under 35 USC 112(b), claims 5 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With regard to claim 5, Ha further discloses,
5. (Original) The stress modulating device of claim 2, wherein:
[1] the first insulating layer [e.g. first silicon oxide sublayer of 804 (supra)] and the third insulating layer [e.g. first silicon oxide sublayer of 806 (supra)] comprise silicon dioxide [supra];
[2] the second insulating layer [e.g. first silicon nitride sublayer of 804 (supra)] and the fifth insulating layer 808 comprise silicon nitride [supra]; and
[3] the fourth insulating layer comprises a SixOyNz composition wherein 1 ≤ x ≤ 3, 0 < y ≤ 2, and 0 < z ≤ 4.
While Ha explains that silicon oxynitride can be used for one of the backside layers having internal tensile stress (Ha: ¶¶ 49, 71), no composition is given. The prior art does not reasonably teach or suggest—in the context of the claim—the “he fourth insulating layer comprises a SixOyNz composition wherein 1 ≤ x ≤ 3, 0 < y ≤ 2, and 0 < z ≤ 4.”
Claim 7 would be allowable for including the same allowable limitation be depending from claim 5, bearing in mind that the limitations of claim 7 are the same as those in claim 6 and therefore disclosed in Ha (supra).
Claims 16-28 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 16 and 21 read,
16. (Previously Presented) A multi-layer semiconductor package assembly comprising:
[1] a first semiconductor device;
[2] a second semiconductor device mounted on the first semiconductor device,
[3] wherein the first semiconductor device is electrically connected to the second semiconductor device,
[4] wherein a combination of the first semiconductor device and the second semiconductor device has an initial stress load; and
[5a] a first stress modulating device configured to reduce the initial stress load, wherein the first stress modulating device comprises:
[5b] a semiconductor substrate;
[5c] a first insulating layer on a first side of the semiconductor substrate;
[5d] a second insulating layer on the first insulating layer;
[5e] a third insulating layer on a second side of the semiconductor substrate;
[5f] a fourth insulating layer on the third insulating layer; and
[5g] a fifth insulating layer on the fourth insulating layer, and
[5h] the stress modulating device is substantially free of conductive materials.
21. (Currently Amended) A multi-layer semiconductor package assembly comprising:
[1] a first semiconductor device;
[2] a second semiconductor device bonded to the first semiconductor device,
[3] wherein the first semiconductor device is electrically connected to the second semiconductor device,
[4] wherein a combination of the first semiconductor device and the second semiconductor device has an initial stress load; and
[5a] a first stress modulating device configured to reduce the initial stress load, wherein the first stress modulating device comprises:
[5b] a substrate;
[5c] a first insulating layer on a first side of the substrate;
[5d] a second insulating layer on the first insulating layer;
[5e] a third insulating layer on a second side of the substrate;
[5f] a fourth insulating layer on the third insulating layer; and
[5g] a fifth insulating layer on the fourth insulating layer,
[5h] wherein the stress modulating device is substantially free of conductive materials.
Each of the limitations of features [5a]-[5h] other than the application of reducing the initial stress load of the first and second semiconductor devices, is taught by Ha, as explained under claim 1. However, Ha discloses that the structure shown in the figures, e.g. Fig. 8 is used for forming a 3D-NAND device (Ha: ¶ 43). In other words, the alternating stack of silicon oxide and silicon nitride 804 formed on the front side of the silicon wafer 803 is processed into said 3D-NAND device. Therefore, one having ordinary skill in the art would not use the stress modulating structure of Ha for attaching first and second semiconductor devices in order to “reduce the initial stress load” caused by said attached first and second semiconductor devices.
The prior art does not reasonably teach or suggest—in the context of the claims—the limitations recited in features [1]-[4] of each of claims 16 and 21.
Claims 17-20 and 22-28 are allowable at least for including the same allowable limitations be depending from one of claims 16 and 21.
VI. Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2002/0064359 (“Ouellet”) is cited for disclosing the same two layers on the front and back sides of a silicon wafer in order to prevent the stresses from causing warping. See entire document.
US 2019/0164912 (“Lee”) is cited for disclosing a stress modulating structure 610, 110, 120, 130, 620 that includes first 300 and second 400 semiconductor devices (Fig. 1) and uses the same materials for the first 110 and third 130 insulating films to control CTE-induced stresses (¶ 26). However, the stress modulating structure 610, 110, 120, 130, 620 includes conductive materials 240 contrary to the limitations in each of independent claims 1, 16, and 21 that the stress modulating structure be substantially free of conductive materials.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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