DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
Determining the scope and contents of the prior art.
Ascertaining the differences between the prior art and the claims at issue.
Resolving the level of ordinary skill in the pertinent art.
Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4 and 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, et al. (US 2020/0373209 A1) in view of Stow et al. (D. Stow, Y. Xie, T. Siddiqua and G. H. Loh, "Cost-effective design of scalable high-performance systems using active and passive interposers," 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Irvine, CA, USA, 2017, pp. 728-735, doi: 10.1109/ICCAD.2017.8203849).
Regarding claim 1, Kim, et al. discloses a method, comprising:
forming first semiconductor dies in a first wafer (Fig. 7, S10);
each die of the first semiconductor dies comprising: first active devices ([0041]) over a front-side of a first semiconductor substrate (Fig.4, 100);
and a first interconnect structure over the first active devices ([0041]);
performing first probe tests on the first wafer ([0016]);
based on the first probe tests, classifying each die of the first semiconductor dies as a first good die or a first bad die (Fig. 4, W1);
forming second semiconductor dies in a second wafer (Fig. 7, S20);
each die of the second semiconductor dies comprising: second active devices over a front-side of a second semiconductor substrate (Fig. 4, 200);
and a second interconnect structure over the second active devices ([0042]);
performing second probe tests on the second wafer; ([0016]);
based on the second probe tests, classifying each die of the second semiconductor dies as a second good die or a second bad die (Fig. 4, W2);
bonding the second wafer to the first wafer, each die of the first semiconductor dies aligning with a corresponding die of the second semiconductor dies (Fig. 7, S30 and Fig. 8, WS).
Kim, et al. lacks the classification of dies as marginal dies based on the probe tests.
However, Stow et al. discloses classifying dies into multiple bins, depending on the number of functional cores detected by the probe (Stow, et al., page 730, section II C, third sentence).
It would have been obvious to a person of ordinary skill in the art before the date of filing to apply Stow et al.’s method of binning dies in multiple categories, including good, marginal (at various levels) and bad, to incorporate more of the probe test information to the die classification in order to improve revenue and produce more functional parts (Stow, et al., page 730, section II B, first paragraph, penultimate sentence).
Regarding claims 2, 3, and 4, Kim et al., in view of Stow et al. discloses the method of claim 1.
Kim et al. as modified lacks:
[claim 2] wherein the first probe tests measure a first number of functional cores in each of the first semiconductor dies, wherein the first number determines a first classification for each of the first semiconductor dies; and
[claim 3] wherein the second probe tests measure a second number of functional cores in each of the second semiconductor dies, wherein the second number determines a second classification for each of the second semiconductor dies; and
[claim 4] determining a third classification for a first exemplary die of the first semiconductor dies and a corresponding second exemplary die of the second semiconductor dies.
However, Stow et al. discloses [claims 2-4] a method wherein leading manufacturers of CPUs, GPUs, and other high-performance circuits rely on binning at the core unit level, i.e. testing and then classifying each semiconductor by the number of functioning cores (Stow, et al., page 730, section II B, first paragraph, penultimate sentence), as well as core-binning for more complex combinations of chips allowing for at least three different classifications (Stow et al., p.731, section II D).
It would have been obvious to a person of ordinary skill in the art before the date of filing to apply Stow et al.’s method of binning dies by number of functioning cores into at least three classifications to the method of claim 1 to improve revenue and produce more functional parts (Stow, et al., page 730, section II B, first paragraph, penultimate sentence and Stow et al., p. 731, section II D).
Regarding claim 8, Kim, et al. discloses a method, comprising:
forming a first wafer comprising first semiconductor dies (Fig. 7, S10);
performing first probe tests on the first semiconductor dies ([0016]);
performing a first binning process to categorize the first semiconductor dies as comprising first good dies and first bad dies (Fig. 4, W1);
forming a second wafer comprising second semiconductor dies (Fig. 7, S20);
performing second probe tests on the second semiconductor dies ([0016]);
performing a second binning process to categorize the second semiconductor dies as comprising second good dies and second bad dies (Fig. 4, W2);
and forming a plurality of semiconductor packages (Fig. 7, bonding the two wafers in step S30 and separating the wafer stack into chip packages in step S40),
the plurality of semiconductor packages comprising: a first high performance package comprising a first one of the first good dies and a first one of the second good dies (Figure 6, known good dies 100 and 200 are bonded to form package 600, which is classified as “A”, denoting a higher performance package);
Kim et al. lacks: a first marginal performance package comprising a first one of the first marginal dies and a first one of the second marginal dies.
However, Stow et al. discloses binning dies into multiple bins, depending on the number of functioning cores (page 730, section II B, first paragraph, penultimate sentence), and then bonding these dies to create multicore processor packages, which are then binned according to performance into multiple bins including a marginal performance “slow” bin (page 731, Table I).
It would have been obvious to a person of ordinary skill in the art before the date of filing to apply Stow et al.’s method of binning both dies and packages comprising two or more dies into multiple categories, including good, marginal (at various levels) and bad, to incorporate more test information to the classifications, in order to improve revenue, produce more functional parts, and reduce the number of unsalvageable chips (page 730, section II B, first paragraph, penultimate sentence; and page 731, section II C, last two sentences).
Regarding claim 9, Kim et al. as modified by Stow et al. discloses the method of claim 8.
Kim et al. further discloses wherein the plurality of the semiconductor packages further comprises a first low performance package comprising a first one of the first bad dies and a first one of the second bad dies (Kim et al. [0027]).
Regarding claim 10, Kim et al. as modified by Stow et al. discloses the method of claim 8. Kim et al. further discloses wherein the plurality of the semiconductor packages further comprises: a second high performance package comprising a second one of the first good dies and a second one of the second marginal dies; and a third high performance package comprising a second one of the first marginal dies and a second one of the second good dies. The reasons the disclosure of Kim et al. applies here are:
The instant application [0020] defines a “good die” as a die that tests above a performance threshold, which equates to the “pass” die of Kim et al. ([0024]).
A “marginal die” as defined by the instant application is a die that tests below a performance threshold of functionality except that being subsequently paired with a die from the second tier being above the performance threshold, it may render the stack of dies sufficiently functional [0020]. The marginal dies are thus a subset of the dies defined by Kim et al as “not pass” dies (Kim et al. [0024]).
“High performance packages” are not defined by the instant application, and thus they may be equated in this discussion with the “packages that pass the package test process”, as defined by Kim et al. [0036].
Regarding the claimed combinations of first and second dies, the “package comprising a second one of the first good dies and a second one of the second marginal dies” is equivalent to the “package comprising a second one of the first marginal dies and a second one of the second good dies,” as the difference between the first and second groups of dies is not indicated.
In Fig. 6, Kim et al. shows a singulated semiconductor package comprising a pass die (100) and a “not pass” die (200), with a package label C, denoting a package that passed the package test process for the package performance ([0038]). The chip shown in this figure is example of a chip produced by a process that is run multiple times creating multiple ‘C’ chips, therefore, reading on the claim language of a second and third high performance packages.
Regarding claim 11, Kim et al. as modified by Stow et al. discloses the method of claim 10. Kim et al. further discloses wherein the plurality of the semiconductor packages further comprises: a second marginal performance package comprising a third one of the first good dies (Fig. 6,100) and a second one of the second bad dies (Fig. 6, 200) In Fig. 6, Kim et al. shows a singulated semiconductor package comprising a pass die (100) and a “not pass” die (200), with a package label C, denoting a “qualified pass” for the package performance [0038]. This disclosure can also read on the claim of a third marginal performance package comprising a second one of the first bad dies and a third one of the second good dies, as Kim et al. note that a plurality of dies from a plurality of wafers are tested ([0024] and [0026]), designated as “pass” or “not pass” ([0024] and [0026]), and bonded to form stacked packages (Fig. 6, 600), which are then classified as “qualified pass”, regardless of the order of stacking, or which chip (100 or 200) was designated “pass” or “non pass” in this combination ([0035]).
Regarding claim 12, Kim et al. as modified by Stow et al. discloses the method of claim 8. Kim et al. further discloses wherein a method of forming the plurality of the semiconductor packages comprises bonding the first wafer to the second wafer. (Fig. 7, S30 and Fig. 8, WS)
Regarding claim 13, Kim et al. as modified by Stow et al. discloses the method of claim 12. Kim et al. further discloses wherein the first high performance package and the first marginal performance package are formed simultaneously in a same wafer and subsequently singulated from one another (Fig. 6 shows a singulated high performance package marked A, comprising two passing dies (100 and 200) and another singulated package comprising a pass die (100) and a “not pass” die (200), with a package label C, denoting a “qualified pass” for the package performance [0038]).
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, et al. as modified by Stow et al., as applied to claim 1 above, and further in view of England et al. (US 2013/0037802 A1).
Regarding claim 5, Kim et al., modified by the method of Stow et al., discloses the method of claim 1.
Kim et al. as modified lacks:
[claim 5] wherein each die of the first semiconductor dies further comprises:
a first through via extending from the front-side of the first semiconductor substrate and partially through the first semiconductor substrate, and
wherein the method further comprises:
attaching a front-side of the first wafer to a carrier substrate; and
removing a portion of the first semiconductor substrate to expose the through via.
[claim 6] wherein bonding the second wafer to the first wafer comprises, after attaching the front-side of the first wafer to the carrier substrate:
forming a first bond pad over the through via; and
forming a direct metal-to-metal bond between the first bond pad and a second bond pad of the second wafer.
[claim 7] attaching a plurality of singulated third semiconductor dies to the second wafer;
removing the carrier substrate; and
forming external connectors along the front-side of the first wafer.
However, England et al. discloses a method wherein
[claim 5] each die of the first semiconductor dies further comprises:
a first through via extending from the front-side of the first semiconductor substrate and partially through the first semiconductor substrate (Fig. 1B, substrate 100 that via 106 extends partially through), and
wherein the method further comprises:
attaching a front-side of the first wafer to a carrier substrate (Fig. 1B, TC is attached to the frontside of wafer/substrate 100); and
removing a portion of the first semiconductor substrate to expose the through via (Fig. 1C, shows a portion of substrate 100 removed to expose via 106).
[claim 6] wherein bonding the second wafer to the first wafer comprises, after attaching the front-side of the first wafer to the carrier substrate:
forming a first bond pad over the through via (1C, bond pad 116 is formed over via 106); and
forming a direct metal-to-metal bond between the first bond pad and a second bond pad of the second wafer (Fig. 1E).
[claim 7] attaching a plurality of singulated third semiconductor dies to the second wafer (Fig. 1I);
removing the carrier substrate (Fig. 1I); and
forming external connectors along the front-side of the first wafer (Fig. 2A, 110).
It would have been obvious to a person of ordinary skill in the art before the date of filing to apply England et al.’s method of bonding semiconductor assemblies to Kim et al.’s bonding method [claim 1] (Kim, et al., Fig. 7, S30 and Fig. 8, WS) in order to efficiently interconnect semiconductor dies to produce smaller chip packages with efficient electrical connection and therefore increase circuit density, which has been an ongoing goal of manufacturers of semiconductor devices (England et al., [0002].
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, et al. as modified by Stow et al., in view of Dabral et al. (US 2020/0176419).
Regarding claim 14, Kim et al. modified by Stow et al. discloses the method of claim 8.
Kim et al. as modified lacks wherein forming the plurality of the semiconductor packages comprises; forming a first reconstructed wafer comprising some of the first semiconductor dies; and attaching a first set of the second semiconductor dies to the first reconstructed wafer.
However, Dabral et al. discloses wherein forming the plurality of the semiconductor packages comprises; forming a first reconstructed wafer comprising some of the first semiconductor dies; and attaching a first set of the second semiconductor dies to the first reconstructed wafer. In Fig. 3, Dabral et al. outline the process of wafer reconstruction comprising mounting a plurality of dies from different wafers ([0048]).
It would have been obvious to a person of ordinary skill in the art before the date of filing to apply Dabral et al.’s method of wafer reconstruction to the method of Kim et al. as modified by Stow et al. to increase the number of high yield packages formed, thus lowering the process cost (Dabral et al. [0086]).
Regarding claim 15, Kim et al. as modified by Stow et al. and Dabral et al. discloses the method of claim 14.
Kim et al. as modified lacks wherein the first high performance package is formed in the first reconstructed wafer, and wherein the first marginal performance package is formed in a second reconstructed wafer being different from the first reconstructed wafer.
However, Dabral et al. discloses wherein the first high performance package is formed in the first reconstructed wafer, and wherein the first marginal performance package is formed in a second reconstructed wafer being different from the first reconstructed wafer. A “marginal die,” as defined by the instant application, is a die that tests below a performance threshold of functionality except that being subsequently paired with a die from the second tier being above the performance threshold, it may render the stack of dies sufficiently functional [0020]. Dabral et al. forms a plurality of reconstituted wafers from a plurality of known good dies (KGDn) that may have a range of levels of acceptable performance ([0060]) and would thus correspond to the instant application’s definition of both good and marginal dies. Since Dabral subsequently bonds the plurality of various reconstituted wafers comprising both good and marginal dies (Fig 19, KGRW1 and KGRWn are bonded in step 1945) to form semiconductor packages (Fig. 19, step 1955), multiple reconstituted wafers comprising lower-performance KGD’s dies would be produced for bonding to create functional packages, thus producing both high and low performance reconstructed wafters that are different depending on the performance of the chips selected to create the reconstructed wafers (Fig. 20 shows various combinations of wafers and processes producing 3D die sets of varying quality; see also [0086]).
It would have been obvious to a person of ordinary skill in the art before the date of filing to apply Dabral et al.’s method of forming multiple reconstituted wafers comprising good dies of various performance levels to the method of Kim et al. as modified by Stow et al. in order to produce functional semiconductor packages of various performance levels at lower cost and with less waste (Dabral et al. [0086] and Fig. 20)
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, et al. in view of England et al.
Regarding claim 16, Kim et al. discloses:
forming a first semiconductor die in a first wafer (Fig. 7, S10);
performing a first binning process to assign a first category to the first semiconductor die (Fig. 4, W1);
forming second semiconductor dies in a second wafer (Fig. 7, S20),
performing a second binning process to assign a second category to the second semiconductor die (Fig. 4, W2);
attaching a front-side of the first wafer to a first carrier substrate (described in the last two sentences of [0043]);
bonding the second semiconductor die to the first semiconductor die (Fig. 3, where first die 100 is bonded to second die 200).
Kim et al. lacks: bonding a third semiconductor die of a plurality of dies to the second semiconductor die, the plurality of dies comprising: sufficient performance dies; and insufficient performance dies, wherein attaching the third semiconductor die comprises selecting between the sufficient performance dies and the insufficient performance dies based on the first category of the first semiconductor die and the second category of the second semiconductor die.
However, England et al. discloses bonding a third semiconductor die of a plurality of dies to the second semiconductor die (Fig. 1F, 120b), the plurality of dies (see paragraph [0027], Fig. 1F 120b) comprising: sufficient performance dies (paragraph [0027]); and insufficient performance dies ([0027]), wherein attaching the third semiconductor die comprises selecting between the sufficient performance dies and the insufficient performance dies based on the first category of the first semiconductor die and the second category of the second semiconductor die. (In Fig. 1F and paragraph [0027], England et al. describe the choice of the third singulated dies (120b) to bond as dependent on whether or not the dies in the first two layers (120u and 120a) are known good dies or bad dies.)
It would have been obvious to a person of ordinary skill in the art before the date of filing to apply England et al.’s method of bonding singulated dies third semiconductor dies, chosen by performance category of the underlying stack, to the die stacks of Kim et al. in order to facilitate precise process control (England et al. [0027] and to minimize packaging costs while the controlling quality and performance of the final chip package England et al. [0014]).
Regarding claim 17, Kim et al. as modified by England discloses the method of claim 16. Kim et al. discloses wherein the insufficient performance dies comprise dummy dies. (The combination of Kim et al. and England et al. produce insufficient performance dies - see above rejection of the last limitation of claim 16. Because these dies are insufficient performance dies, they would qualify as dummy dies – See England et al. [0027] for discussion of stacking bad dies to facilitate precise process control.)
Regarding claim 18, Kim et al. as modified by England discloses the method of claim 16.
Kim et al. as modified lacks: wherein one of the sufficient performance dies is selected if at least one of the first category or the second category is above a predetermined performance threshold, and wherein one of the insufficient performance dies is selected if both the first category and the second category are below the predetermined performance threshold.
However, England et al. discloses wherein one of the sufficient performance dies is selected if at least one of the first category or the second category is above a predetermined performance threshold, and wherein one of the insufficient performance dies is selected if both the first category and the second category are below the predetermined performance threshold. (In Fig. 1F and paragraph [0027], England et al. describe the choice of the third singulated dies (120b) to bond as dependent on whether or not the dies in the first two layers (120u and 120a) are known good dies or bad dies.)
It would have been obvious to a person of ordinary skill in the art before the date of filing to apply England et al.’s method of bonding singulated dies third semiconductor dies, chosen by performance category of the underlying stack, to the die stacks of Kim et al. as modified by England et al. [claim 16] in order to facilitate precise process control (England et al. [0027] and to minimize packaging costs while the controlling quality and performance of the final chip package (England et al. [0014].
Regarding claim 19, Kim et al. as modified by England discloses the method of claim 16.
Kim et al. lacks wherein the first semiconductor die, the second semiconductor die, and the third semiconductor die combine to form a semiconductor package.
However, England et al., disclose a semiconductor comprising at least three stacked dies (Fig 2A).
It would have been obvious to a person of ordinary skill in the art before the date of filing to apply England et al.’s method of stacking more than two dies to the die stacks of Kim et al. in order to increase circuit density, which has been an ongoing goal of manufacturers of semiconductor devices (England et al. [0002]).
Regarding claim 20, Kim et al. as modified by England discloses the method of claim 19. Kim et al. discloses further comprising a third binning process to assign the semiconductor package to a third category. Kim et al. disclose a method wherein stacked semiconductor packages, each comprising a plurality of chips, are tested and assigned to a third category according to the performance of the stacked package as a whole [0038-0039].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Rathert et al. (US Publication 2022/0260632) discloses creating ranked semiconductor packages with different performance metrics; also, Osann et al. (6399400), Kim et al. (US Publication 2023/0028219), Lin et al. (9941207) all disclose various methods of binning semiconductor packages.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATRINA M H WALJESKI-MOSES whose telephone number is (571)272-0731. The examiner can normally be reached Mon- Thu. 7:00 am- 4 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KATRINA WALJESKI-MOSES/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818