Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 05/12/2026 have been fully considered but they are not persuasive.
Regarding independent claim 1, the Applicant’s arguments are respectfully traversed. The Applicant asserts that Stow does not discuss provide any discussion to explain how a third classification may be determined and utilized for a combination of a first die and a second die as recited in amended claim 1.
In response to applicant's arguments against the teachings of Stow individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986), MPEP 2145(IVG). In this case, Kim discloses all the limitations of the first amended claim, as discussed in the non-final rejection. Only the sorting into a number of bins greater than two is lacking in Kim’s disclosure. Stow explicitly teaches the example of binning of packages of dies into groups based on number of functioning cores: for example, Stow teaches at least 3 bins for two-chip packages (2 functioning cores, one functioning core/one non-functioning core , and two non-functioning cores) that may correspond to the claimed “good”, “marginal”, and “bad” classifications. Stow’s disclosure of using 3 or more bins for sorting chip packages by probe test results is obvious to combine with Kim’s disclosure of methods of sorting dies and die packages, as Stow’s disclosure is in the same field of endeavor, testing and binning of chips and chip packages, as that of Kim; and it would have been obvious to a person having ordinary skill in the art at the time of filing to expand the number of bins from Kim’s 2 bins to the three bins taught by Stow in order to incorporate more information from the probe tests into the binning process to allow for fabrication of chip packages more precisely matched to the required specifications of the application, therefore increasing cost effectiveness. All the limitations of claim 1 are disclosed in either Kim or Stow, and the combination of these references renders the claimed invention obvious: therefore, the Applicant’s arguments are not persuasive and the rejection of independent claim 1 is maintained.
Regarding independent claim 8, the Applicant’s arguments are respectfully traversed. The Applicant argues that neither Kim nor Stow provides any specific disclosure of pairing a die categorized as "marginal" with another die categorized as "marginal" to form a marginal package and that assuming such a teaching would require reading additional information into the respective disclosures is improper hindsight in order to reject claim 8.
In response to the Applicant’s argument that neither Stow nor Kim teaches pairing marginal dies to form marginal packages: Stow explicitly teaches three-bin sorting as described in the response to arguments regarding amended claim 1 above. Although Stow does not call a middle bin “marginal”, chiplets classified in the bin between the best bin and the worst bin may reasonably be considered to be “marginal”. In regard to the binning of packages, in section C on page 731, Stow discloses sorting packages comprising previously binned chips into multiple bins according to package performance, including “slow” performance bins, corresponding to the instant application’s “marginal performance” bins in that they are functional (not “bad”) but not in the target performance range (not “high performance”). Therefore, in combination, Kim and Stow teach all the limitations of amended claim 8, including pairing of “marginal” dies to form “marginal performance” packages, as is described in detail in the rejection of amended claim 8.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
The rejection of independent claim 8 is therefore maintained.
Regarding dependent claim 10, the Applicant’s arguments are respectfully traversed.
In response to Applicant’s argument regarding matter from the specification, it is noted that although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
In response to Applicant’s argument that Kim's binary system cannot teach specific pairings of a good die with a marginal die and a marginal die with a good die to form two distinctive high performance packages, without attributing improper hindsight: Kim as modified by Stow discloses the limitations of claim 10, and the reasons that the disclosure of Kim as modified by Stow is applicable to the claim 10 are described in detail in the rejection of claim 10 in the non-final rejection of the instant application. Applicant’s argument is not persuasive, as one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Regarding the Applicant’s assertion of the use of improper hindsight, as before, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
The rejection of dependent claim 10 is therefore maintained.
Regarding dependent claim 11, the Applicant contends that it is improper to use a single portion of the disclosure of Kim to map different claim features in the rejections of claim 10 and the rejection of claim 11.
Firstly, the disclosure of Kim alone is not used to reject either claim 10 or claim 11. Again, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Rather, as described in the non-final rejection, teachings of Kim in view of Stow are used to show that all the limitations of claims 10 and 11 are rendered obvious by this prior art: therefore, the Applicant’s argument is not persuasive.
Secondly, it is the broadest reasonable interpretation (BRI) of claims 10 and 11 that is rendered obvious by the combination of Kim and Stow. During patent examination, the pending claims must be "given their broadest reasonable interpretation consistent with the specification." The Federal Circuit’s en banc decision in Phillips v. AWH Corp., 415 F.3d 1303, 1316, 75 USPQ2d 1321, 1329 (Fed. Cir. 2005) expressly recognized that the USPTO employs the "broadest reasonable interpretation." See also In re Suitco Surface, Inc., 603 F.3d 1255, 1259, 94 USPQ2d 1640, 1643 (Fed. Cir. 2010); In re Hyatt, 211 F.3d 1367, 1372, 54 USPQ2d 1664, 1667 (Fed. Cir. 2000). The BRI of both claims 10 and 11, as described in the non-final office action’s rejections of these claims, may be rendered obvious by the combination of Kim and Stow: therefore, the Applicant’s argument is not persuasive.
In response to applicant's argument that it is improper to use obviousness over the same prior art to reject multiple claims: the test for obviousness is not that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). In this case, the same portion of the prior art of Kim in view of Stow would have rendered obvious the BRI’s of both claims 10 and 11, as described in the non-final rejection, to a person reasonably skilled in the art, so the rejections of both claims are proper, and therefore the Applicant’s argument is not persuasive.
There is no requirement for consistency in the application of the prior art reject multiple claims if the teachings of that same prior art render multiple claims obvious. For example, Kim’s sorting of chips into binary binning categories, in view of Stow’s multiple-bin sorting procedure, could comprise multiple bins, including the “good”, “marginal”, and “bad” of the instant application, as the claims do not distinctly point out and claim the criteria defining those labels. Similarly, claims 10 and 11 fail to point out and distinctly claim the attributes of “high performance” and “marginal performance” packages. The criteria for sorting and the definitions of the bins are not well-defined in each of the claims; therefore, there is nothing in these claims requiring a specific and unchanging mapping of the prior art between each of the claims. Thus, the BRI of each of these claims is properly be shown to be rendered obvious by the same combination of prior art without any inconsistency. Therefore, the Applicant’s argument is not persuasive.
The rejection of dependent claim 11 is therefore maintained.
Regarding dependent claims 14 and 15, Applicant argues that the Office Action fails to make a prima facie case of obviousness.
In response to applicant’s argument that that the Office Action fails to make a prima facie case of obviousness because there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, the use of methods of sorting, binning, and grouping chips and semiconductor packages, as well as combining these techniques with various processor fabrication techniques to improve the efficiency and economy of processor production are well known to those with ordinary skill in the art, and these motivations are disclosed by the references themselves, as described in the non-final rejection, therefore the Applicant’s argument is not persuasive.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971). A person of ordinary skill in the art at the time of filing would have been well aware of the economic incentives to match the semiconductor packages produced by any means to the market demand by using the sorting and binning techniques of Kim.
Further, the applicant contends that the combination of Dabral with Kim is improper because it is improper to apply Dabral's wafer reconstruction methodology to Kim's testing methodology, as Kim's testing methodology applies to the context of a "wafer level bonding-based semiconductor package" formation.
In response to applicant's argument that the combination of Dabral and Kim is improper, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). It would be reasonable to use the sorting and binning methods of Kim, with semiconductor packages produced by any bonding method, including the method disclosed by Dabral, to produce semiconductor packages with selected attributes, which will predictably produce these packages to meet specific market demand, thereby improving profit and reducing waste; therefore, the Applicant’s argument is not persuasive.
The rejection of dependent claims 14 and 15 is therefore maintained.
Regarding independent claim 16, the Applicant contends that a proper combination of Kim and England fails to teach the features recited in claim 16. In particular, the Applicant argues that England discloses attaching the KGDs or bad dies based on the testing results of the un-singulated dies, but the Applicant contends that England does not disclose this process step as being also based on testing of the already-attached dies as required in claim 16. The Applicant further argues that applying England's disclosure to Kim's process would be based on a testing of Kim's semiconductor packages rather than distinct testing of Kim's chips.
In response to the assertion that England fails to disclose the process of testing the already attached dies, England discloses in paragraph [0027] that the attached dies qualify as “Known Good Dies’ or “bad un-singulated dies” , which implicitly discloses that testing and binning of those dies has been done previously (England [0027]); therefore, the Applicant’s argument is not persuasive.
In response to the Applicants argument that applying England's disclosure to Kim's process would be based on a testing of Kim's semiconductor packages rather than distinct testing of Kim's chips. Here, again, in order to test designate the individual chips as KGDs or bad dies must be performed on the individual dies themselves. In paragraph [0025-0026] Kim says that packages 600 comprise chips that are known to be good or bad chips, which implicitly discloses distinct testing of Kim’s chips; therefore, the Applicant’s argument is not persuasive.
The rejection of independent claim 16 is therefore maintained.
Response to Amendment
Claim Objections
Claim 1 is objected to because of the following informalities:
It is recommended that claim 1 in the amended portion state “determining a first [[third]] classification….” Because in claim 1, first and second classifications are not described (because this limitation is coming from previous claim 4), those are now only found in dependent claims. It would then be recommended to adjust the dependent claims accordingly. This is not required, but wanted to make Applicant aware of this as it would make independent claim 1 flow better.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 22 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. There is no support for “bonding third semiconductor dies to the second semiconductor dies based on the first binning process and the second binning process” in the disclosure. There is “a plurality of singulated third semiconductor dies” in claim 7 and supported in the specifications [0067]. In claim 16 there is “a third semiconductor die of a plurality of dies” claimed and further limited; however, this is not related to what is claimed in claim 22. Therefore claim 22 includes new matter.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 22 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. There is no description of the claimed “third semiconductor dies” or their relationship to the first and second binning processes. The “plurality of semiconductor packages” of claim 8 (amended) comprise three packages: a first high performance package comprising a first one of the first good dies and a first one of the second good dies, a first marginal performance package comprising a first one of the first marginal dies and a first one of the second marginal dies, and a first low performance package comprising a first one of the first bad dies and a first one of the second bad dies. Claim 22 adds the limitation: wherein forming the plurality of semiconductor packages further comprises bonding third semiconductor dies to the second semiconductor dies based on the first binning process and the second binning process. As the first and second binning processes are described, they do not apply to the third semiconductor dies.
For the purpose of compact examination, the third semiconductors will be assumed to be another set of semiconductor dies analogous to the first semiconductor dies of claim 8 (amended).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-3, 8, 10-13 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, et al. (US 2020/0373209 A1) in view of Stow et al. (2017 article presented in the previous office action).
Regarding claims 1, 2 and 3, Kim discloses a method, comprising:
forming first semiconductor dies in a first wafer (Fig. 7, S10);
each die of the first semiconductor dies comprising: first active devices ([0041]) over a front-side of a first semiconductor substrate (Fig.4, 100);
and a first interconnect structure over the first active devices ([0041]);
performing first probe tests on the first wafer ([0016]);
based on the first probe tests, classifying each die of the first semiconductor dies as a first good die or a first bad die (Fig. 4, W1);
forming second semiconductor dies in a second wafer (Fig. 7, S20);
each die of the second semiconductor dies comprising: second active devices over a front-side of a second semiconductor substrate (Fig. 4, 200);
and a second interconnect structure over the second active devices ([0042]);
performing second probe tests on the second wafer; ([0016]);
based on the second probe tests, classifying each die of the second semiconductor dies as a second good die or a second bad die (Fig. 4, W2);
bonding the second wafer to the first wafer, each die of the first semiconductor dies aligning with a corresponding die of the second semiconductor dies (Fig. 7, S30 and Fig. 8, WS).
Kim lacks:
[claim 1] the classification of dies as marginal dies based on the probe tests and determining a third classification for a first exemplary die of the first semiconductor dies and a corresponding second exemplary die of the second semiconductor dies.
[claim 2] wherein the first probe tests measure a first number of functional cores in each of the first semiconductor dies, wherein the first number determines a first classification for each of the first semiconductor dies; and
[claim 3] wherein the second probe tests measure a second number of functional cores in each of the second semiconductor dies, wherein the second number determines a second classification for each of the second semiconductor dies;
However, Stow discloses
[claim 1] classifying dies into multiple bins, depending on the number of functional cores detected by the probe (Stow, page 730, section Il C, third sentence), and
[claims 1, 2, and 3] a method wherein leading manufacturers of CPUs, GPUs, and other high-performance circuits rely on binning at the core unit level, i.e. testing and then classifying each semiconductor by the number of functioning cores (Stow page 730, section II B, first paragraph, penultimate sentence), as well as core-binning for more complex combinations of chips allowing for at least three different classifications (Stow p.731, section II D).
It would have been obvious to a person of ordinary skill in the art before the date of filing to apply Stow's method of binning dies in multiple categories, including good, marginal (at various levels) and bad, and Stow’s method of binning dies by number of functioning cores into at least three classifications to incorporate more of the probe test information to the die classification in order to improve revenue and produce more functional parts (Stow page 730, section II B, first paragraph, penultimate sentence).
Regarding claim 8, Kim discloses a method, comprising:
forming a first wafer comprising first semiconductor dies (Fig. 7, S10);
performing first probe tests on the first semiconductor dies ([0016]);
performing a first binning process to categorize the first semiconductor dies as comprising first good dies and first bad dies (Fig. 4, W1);
forming a second wafer comprising second semiconductor dies (Fig. 7, S20);
performing second probe tests on the second semiconductor dies ([0016]);
performing a second binning process to categorize the second semiconductor dies as comprising second good dies and second bad dies (Fig. 4, W2);
and forming a plurality of semiconductor packages (Fig. 7, bonding the two wafers in step S30 and separating the wafer stack into chip packages in step S40),
the plurality of semiconductor packages comprising: a first high performance package comprising a first one of the first good dies and a first one of the second good dies (Figure 6, known good dies 100 and 200 are bonded to form package 600, which is classified as "A", denoting a higher performance package); and
a first low performance package comprising a first one of the first bad dies and a first one of the second bad dies (Kim [0024-0027] and [0030]).
Kim lacks a first marginal performance package comprising a first one of the first marginal dies and a first one of the second marginal dies.
However, Stow discloses binning dies into multiple bins, depending on the number of functioning cores (page 730, section II B, first paragraph, penultimate sentence), and then bonding these dies to create multicore processor packages, which are then binned according to performance into multiple bins including a marginal performance "slow" bin (page 731, Table I).
It would have been obvious to a person of ordinary skill in the art before the date of filing to apply Stow's method of binning both dies and packages comprising two or more dies into multiple categories, including good, marginal (at various levels) and bad, to incorporate more test information to the classifications, in order to improve revenue, produce more functional parts, and reduce the number of unsalvageable chips (page 730, section II B, first paragraph, penultimate sentence; and page 731, section Il C, last two sentences).
Regarding claim 10, Kim as modified by Stow discloses the method of claim 8(amended). Kim further discloses wherein the plurality of the semiconductor packages further comprises:
a second high performance package comprising a second one of the first good dies and
a second one of the second marginal dies; and
a third high performance package comprising a second one of the first marginal dies and a second one of the second good dies.
The reasons the disclosure of Kim applies here are:
Under BRI, the “good die” of the instant application [0020] may correspond to the "pass" die of Kim ([0024]).
Also under BRI, "marginal dies", defined by the instant application as dies that may test below a performance threshold of functionality except that one being subsequently paired with a die from the second tier being above the performance threshold may render the stack of dies sufficiently functional [0020], may be considered to be a subset of the dies defined by Kim as "not pass" dies (Kim [0024])
"High performance packages" are not defined by the instant application, and thus they may be equated in this discussion with the "packages that pass the package test process", as defined by Kim [0036].
Regarding the claimed combinations of first and second dies, the "package comprising a second one of the first good dies and a second one of the second marginal dies" is equivalent to the "package comprising a second one of the first marginal dies and a second one of the second good dies," as the differences between the first and second groups of dies are not indicated.
In Fig. 6, Kim shows a singulated semiconductor package comprising a pass die (100) and a "not pass" die (200), with a package label C, denoting a package that passed the package test process for the package performance ([0038]). The chip shown in this figure is example of a chip produced by a process that is run multiple times creating multiple 'C' chips, therefore, reading on the claim language of a second and third high performance packages.
Regarding claim 11, Kim as modified by Stow discloses the method of claim 10. Kim further discloses wherein the plurality of the semiconductor packages further comprises: a second marginal performance package comprising a third one of the first good dies (Fig. 6,100) and a second one of the second bad dies (Fig. 6, 200)
Fig. 6, shows a singulated semiconductor package comprising a pass die (100) and a "not pass" die (200), with a package label C, denoting a "qualified pass" for the package performance [0038]. This disclosure can also read on the claim of a third marginal performance package comprising a second one of the first bad dies and a third one of the second good dies, as Kim notes that a plurality of dies from a plurality of wafers are tested ([0024] and [0026]), designated as "pass" or "not pass" ([0024] and [0026]), and bonded to form stacked packages (Fig. 6, 600), which are then classified as "qualified pass", regardless of the order of stacking, or
which chip (100 or 200) was designated "pass" or "non pass" in this combination ([0035]).
Regarding claim 12, Kim as modified by Stow discloses the method of claim 8(amended). Kim further discloses wherein a method of forming the plurality of the semiconductor packages comprises bonding the first wafer to the second wafer. (Fig. 7, S30 and Fig. 8, WS)
Regarding claim 13, Kim as modified by Stow discloses the method of claim 12. Kim further discloses wherein the first high performance package and the first marginal performance package are formed simultaneously in a same wafer and subsequently singulated from one another (Fig. 6 shows a singulated high performance package marked A, comprising two passing dies (100 and 200) and another singulated package comprising a pass die (100) and a "not pass" die (200), with a package label C, denoting a "qualified pass" for the package performance [0038]).
Regarding claim 22, Kim as modified by Stow discloses the method of claim 8, wherein forming the plurality of semiconductor packages further comprises bonding third semiconductor dies to the second semiconductor dies based on the first binning process and the second binning process. See the rejection of claim 8 – since the third semiconductor dies can be analogous to the first semiconductor dies of claim 8 (see the 112(b) rejection of claim 22 above), then the rejection of this claim is analogous to that of claim 8 above – meaning that the first semiconductor dies will be a group of dies, without further limitations imposed on a third group of semiconductor dies (specific description/structure) that would disallow some of the first semiconductor dies to be considered third semiconductor dies, some of the first semiconductor dies could be considered both first and third semiconductor dies or could only be considered third semiconductor dies.
Claims 5-7, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as modified by Stow as applied to claim 1(amended) above, and further in view of England et al. (US 2013/0037802 A1).
Regarding claims 5, 6, and 7, Kim as modified by Stow, discloses the method of claim 1(amended).
Kim as modified lacks:
[claim 5] wherein each die of the first semiconductor dies further comprises: a first through via extending from the front-side of the first semiconductor substrate and partially through the first semiconductor substrate, and wherein the method further comprises: attaching a front-side of the first wafer to a carrier substrate; and removing a portion of the first semiconductor substrate to expose the through via.
[claim 6] wherein bonding the second wafer to the first wafer comprises, after attaching the front-side of the first wafer to the carrier substrate: forming a first bond pad over the through via; and forming a direct metal-to-metal bond between the first bond pad and a second bond pad of the second wafer.
[claim 7] attaching a plurality of singulated third semiconductor dies to the second wafer; removing the carrier substrate; and forming external connectors along the front-side of the first wafer.
However, England. discloses a method wherein:
[claim 5] each die of the first semiconductor dies further comprises: a first through via extending from the front-side of the first semiconductor substrate and partially through the first semiconductor substrate (Fig. 1B, substrate 100 that via 106 extends partially through), and wherein the method further comprises: attaching a front-side of the first wafer to a carrier substrate (Fig. 1B, TC is attached to the frontside of wafer/substrate 100); and removing a portion of the first semiconductor substrate to expose the through via (Fig. 1C, shows a portion of substrate 100 removed to expose via 106
[claim 6] wherein bonding the second wafer to the first wafer comprises, after attaching the front-side of the first wafer to the carrier substrate: forming a first bond pad over the through via (1C, bond pad 116 is formed over via 106); and forming a direct metal-to-metal bond between the first bond pad and a second bond pad of the second wafer (Fig. 1E)
[claim 7] attaching a plurality of singulated third semiconductor dies to the second wafer (Fig. 1I); removing the carrier substrate (Fig. 1I); and forming external connectors along the front-side of the first wafer (Fig. 2A, 110).
It would have been obvious to a person of ordinary skill in the art before the date of filing to apply England's method of bonding semiconductor assemblies to Kim's bonding method [claim 1(amended)] (Kim Fig. 7, S30 and Fig. 8, WS) in order to efficiently interconnect semiconductor dies to produce smaller chip packages with efficient electrical connection and therefore increase circuit density, which has been an ongoing goal of manufacturers of semiconductor devices (England [0002].
Regarding claim 21, Kim as modified by Stow as applied to claim 1 above, and further in view of England discloses the method of claim 7, wherein the plurality of singulated third semiconductor dies comprises: sufficient performance dies (England paragraph [0027]); and insufficient performance dies (England [0027]), wherein attaching the plurality of singulated third semiconductor dies comprises selecting between the sufficient performance dies and the insufficient performance dies based on the first probe tests and the second probe tests (In Fig. 1F and paragraph [0027], England describe the choice of the third singulated dies (120b) to bond as dependent on whether or not the dies in the first two layers (120u and 120a) are known good dies or bad dies. Dies are already known to be good or bad dies based on probe tests (see the rejection of claim 1).
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as modified by Stow, in view of Dabral et al. (US 2020/0176419).
Regarding claim 14, Kim modified by Stow discloses the method of claim 8(amended).
Kim as modified lacks wherein forming the plurality of the semiconductor packages comprises; forming a first reconstructed wafer comprising some of the first semiconductor dies; and attaching a first set of the second semiconductor dies to the first reconstructed wafer.
However, Dabral discloses wherein forming the plurality of the semiconductor packages comprises; forming a first reconstructed wafer comprising some of the first semiconductor dies; and attaching a first set of the second semiconductor dies to the first reconstructed wafer. In Fig. 3, Dabral outlines the process of wafer reconstruction comprising mounting a plurality of dies from different wafers ([0048]).
It would have been obvious to a person of ordinary skill in the art before the date of filing to apply Dabral’s method of wafer reconstruction to the method of Kim. as modified by Stow to increase the number of high yield packages formed, thus lowering the process cost (Dabral [0086]).
Regarding claim 15, Kim as modified by Stow and Dabral discloses the method of claim 14.
Kim as modified lacks wherein the first high performance package is formed in the first reconstructed wafer, and wherein the first marginal performance package is formed in a second reconstructed wafer being different from the first reconstructed wafer.
However, Dabral discloses wherein the first high performance package is formed in the first reconstructed wafer, and wherein the first marginal performance package is formed in a second reconstructed wafer being different from the first reconstructed wafer. A "marginal die," under BRI, is a die that tests below a performance threshold of functionality except that being subsequently paired with a die from the second tier being above the performance threshold, it may render the stack of dies sufficiently functional [0020]. Dabral forms a plurality of reconstituted wafers from a plurality of known good dies (KGD’s) that may have a range of levels of acceptable performance ([0060]) and would thus correspond to both the instant
application's good and marginal dies . Since Dabral subsequently bonds the plurality of various reconstituted wafers comprising both good and marginal dies (Fig 19, KGRW1 and KGRWn are bonded in step 1945) to form semiconductor packages (Fig. 19, step 1955), multiple reconstituted wafers comprising lower- performance KGD's dies would be produced for bonding to create functional packages, thus producing both high and low performance reconstructed wafters that are different depending on the performance of the chips selected to create the reconstructed wafers (Fig. 20 shows various combinations of wafers and processes producing 3D die sets of varying quality; see also [0086]).
It would have been obvious to a person of ordinary skill in the art before the date of filing to apply Dabral's method of forming multiple reconstituted wafers comprising good dies of various performance levels to the method of Kim as modified by Stow in order to produce functional semiconductor packages of various performance levels at lower cost and with less waste (Dabral [0086] and Fig. 20).
Claims 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of England.
Regarding claim 16, discloses:
forming a first semiconductor die in a first wafer (Fig. 7, S10);
performing a first binning process to assign a first category to the first semiconductor die (Fig. 4, W1);
forming second semiconductor dies in a second wafer (Fig. 7, S20),
performing a second binning process to assign a second category to the second semiconductor die (Fig. 4, W2);
attaching a front-side of the first wafer to a first carrier substrate (described in the last two sentences of [0043]);
bonding the second semiconductor die to the first semiconductor die (Fig. 3, where first die 100 is bonded to second die 200).
Kim lacks: bonding a third semiconductor die of a plurality of dies to the second semiconductor die, the plurality of dies comprising: sufficient performance dies; and insufficient performance dies, wherein attaching the third semiconductor die comprises selecting between the sufficient performance dies and the insufficient performance dies based on the first category of the first semiconductor die and the second category of the second semiconductor die.
However, England discloses bonding a third semiconductor die of a plurality of dies to the second semiconductor die (Fig. 1F, 120b), the plurality of dies (see paragraph [0027], Fig. 1F 120b) comprising: sufficient performance dies (paragraph [0027]); and insufficient performance dies ([0027]), wherein attaching the third semiconductor die comprises selecting between the sufficient performance dies and the insufficient performance dies based on the first category of the first semiconductor die and the second category of the second semiconductor die. (In Fig. 1F and paragraph [0027], England describe the choice of the third singulated dies (120b) to bond as dependent on whether or not the dies in the first two layers (120u and 120a) are known good dies or bad dies.)
It would have been obvious to a person of ordinary skill in the art before the date of filing to apply England's method of bonding singulated dies third semiconductor dies, chosen by performance category of the underlying stack, to the die stacks of Kim in order to facilitate precise process control (England [0027] and to minimize packaging costs while the controlling quality and performance of the final chip package England [0014]).
Regarding claim 17, Kim as modified by England discloses the method of claim 16. Kim discloses wherein the insufficient performance dies comprise dummy dies. (The combination of the methods of Kim and England produce insufficient performance dies - see above rejection of the last limitation of claim 16. Because these dies are insufficient performance dies, they would qualify as dummy dies - See England [0027] for discussion of stacking bad dies to facilitate precise process control.)
Regarding claim 18, Kim as modified by England discloses the method of claim 16.
Kim as modified lacks: wherein one of the sufficient performance dies is selected if at least one of the first category or the second category is above a predetermined performance threshold, and wherein one of the insufficient performance dies is selected if both the first category and the second category are below the predetermined performance threshold.
However, England discloses wherein one of the sufficient performance dies is selected if at least one of the first category or the second category is above a predetermined performance threshold, and wherein one of the insufficient performance dies is selected if both the first category and the second category are below the predetermined performance threshold. (In Fig. 1F and paragraph [0027], England describes the choice of the third singulated dies (120b) to bond as dependent on whether or not the dies in the first two layers (120u and 120a) are known good dies or bad dies.)
It would have been obvious to a person of ordinary skill in the art before the date of filing to apply England's method of bonding singulated third semiconductor dies, chosen by performance category of the underlying stack, to the die stacks of Kim as modified by England [claim 16] in order to facilitate precise process control (England [0027] and to minimize packaging costs while the controlling quality and performance of the final chip package (England [0014].
Regarding claim 19, Kim as modified by England discloses the method of claim 16.
Kim lacks wherein the first semiconductor die, the second semiconductor die, and the third semiconductor die combine to form a semiconductor package.
However, England, disclose a semiconductor comprising at least three stacked dies (Fig 2A).
It would have been obvious to a person of ordinary skill in the art before the date of filing to apply England's method of stacking more than two dies to the die stacks of Kim in order to increase circuit density, which has been an ongoing goal of manufacturers of semiconductor devices (England [0002]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action (noting that the same rejection is used for amended claims 1 and 8 being that only dependent claims were moved into those claims – but new claims 21 and 22 required a new rejection). Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a).
Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATRINA M H WALJESKI-MOSES whose telephone number is (571)272-0731. The examiner can normally be reached Mon- Fri 7:30 am- 4 pm.
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/KATRINA WALJESKI-MOSES/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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