DETAILED ACTION
This action is responsive to the application No. 18/459,448 filed on September 01, 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the Species 2 invention reading on Fig. 17 in the reply filed on 01/02/2026 is acknowledged. The Applicants indicated that claims 1-20 read on the elected species. Accordingly, pending in this Office action are claims 1-20.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation “the first conductive via”. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 8, 10, 12-16, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liaw (US 2022/0328499).
Regarding Claim 1, Liaw (see, e.g., Figs. 2-2, 3, 8-9), teaches a semiconductor device, comprising:
a first transistor W_PU-1 (see, e.g., par. 0025), comprising:
a first gate structure 240 (see, e.g., par. 0030);
a first channel structure 215, overlapping with the first gate structure 240 (see, e.g., par. 0030);
a first source/drain feature 260N and a second source/drain feature 260N, electrically connected with the first channel structure 215 (see, e.g., par. 0048);
a first source/drain contact 406 and a second source/drain contact 406, respectively electrically connected with the first source/drain feature 260N and the second source/drain feature 260N (see, e.g., par. 0058);
a second transistor W_PD-2 (see, e.g., par. 0025), comprising:
a second gate structure 240 (see, e.g., par. 0030);
a second channel structure 215, overlapping with the second gate structure 240 (see, e.g., par. 0030); and
an interconnect structure 270/409, disposed over the first transistor W_PU-1 and the second transistor W_PD-2 (see, e.g., pars. 0059-0060),
wherein the interconnect structure 270/409 comprises:
a first conductive via 409, electrically connecting the first source/drain contact 406 to the second gate structure 240, and in contact with a top surface of the first source/drain contact 406 and a side surface of the first source/drain contact 406 (see, e.g., par. 0032).
Regarding Claim 2, Liaw teaches all aspects of claim 1. Liaw (see, e.g., Figs. 2-2, 3, 8-9), teaches that the first conductive via 409 is in contact with a top surface of the second gate structure 240.
Regarding Claim 3, Liaw teaches all aspects of claim 1. Liaw (see, e.g., Figs. 2-2, 3, 8-9), teaches that the first source/drain contact 406 and the second source/drain contact 406 are embedded in an interlayer dielectric layer 270 disposed above the first source/drain feature 260N and the second source/drain feature 260N, and the first conductive via 409 extends from a top surface of the interlayer dielectric layer 270 into the interlayer dielectric layer 270 (see, e.g., par. 0059).
Regarding Claim 8, Liaw teaches all aspects of claim 1. Liaw (see, e.g., Figs. 2-2, 3, 8-9), teaches a dummy channel structure 215 laterally located between the second gate structure 240 and the first source/drain feature 260N.
Regarding Claim 10, Liaw (see, e.g., Figs. 1B, 2-2, 3, 8-9), teaches a static random access memory (SRAM) cell, comprising:
a first pull-up gate-all-around (GAA) transistor W_PU-1 and a first pull-down GAA transistor W_PD-1 coupled together to form a first inverter (see, e.g., par.0025);
a second pull-up GAA transistor W_PU-2 and a second pull-down GAA transistor W_PD-2 coupled together to form a second inverter (see, e.g., par.0025);
a first pass-gate GAA transistor W_PG-1 coupled to an output of the first inverter and an input of the second inverter (see, e.g., par.0025); and
wherein a source/drain contact 406 of the first pull-up GAA transistor W_PU-1 is electrically connected with a gate structure 240 of the second pull-down GAA transistor W_PD-2 through a conductive feature 409 of an interconnect structure 270/408/409, wherein the conductive feature 409 is in contact with a top surface of the source/drain contact 406 and a side surface of the source/drain contact 406 (see, e.g., pars.0025, 0058).
Regarding Claim 12, Liaw teaches all aspects of claim 10. Liaw (see, e.g., Figs. 1, 2-2, 3, 8-9), teaches that the source/drain contact 406 is surrounded by an interlayer dielectric layer 408 (see, e.g., par. 0057).
Regarding Claim 13, Liaw teaches all aspects of claim 10. Liaw (see, e.g., Figs. 1, 2-2, 3, 8-9), teaches that the interconnect structure 270/408/409 comprises:
a first protective layer 408, disposed above the gate structure 240 of the second pull-down GAA transistor W_PD-2 (see, e.g., par. 0057);
a first insulation layer 270, disposed above the first protective layer 408, wherein the first conductive via 409 is penetrating through the first protective layer 408 and the first insulation layer 270 (see, e.g., par. 0059).
Regarding Claim 14, Liaw (see, e.g., Figs. 2-2, 3, 8-9), teaches a semiconductor structure, comprising:
a first gate-all-around (GAA) structure 215 located between a first source/drain feature 260N and a second source/drain feature 260N (see, e.g., pars. 0030, 0048);
a first gate electrode 350 surrounding the first GAA structure 215 (see, e.g., par. 0054);
a first source/drain contact 406 and a second source/drain contact 406, respectively disposed above the first source/drain feature 260N and the second source/drain feature 260N (see, e.g., par. 0058);
a second gate electrode 350, wherein the first source/drain feature 260N is located between the first gate electrode 350 and the second gate electrode 350 (see, e.g., par. 0054);
a conductive feature 409 disposed above the first source/drain contact 406 and the second gate electrode 350, and the conductive feature 409 electrically connects the first source/drain contact 406 to the second gate electrode 350, wherein the conductive feature 409 is extending along a portion of a top surface of the first source/drain contact 406 and a portion of a side surface of the first source/drain contact 406 (see, e.g., par. 0032).
Regarding Claim 15, Liaw teaches all aspects of claim 14. Liaw (see, e.g., Figs. 2-2, 3, 8-9), teaches a dummy channel structure 215 laterally located between the second gate electrode 350 and the first source/drain feature 260N.
Regarding Claim 16, Liaw teaches all aspects of claim 15. Liaw (see, e.g., Figs. 2-2, 3, 8-9), teaches a gate dielectric layer 282, disposed between the first GAA structure 215 and the first gate electrode 350 and between the dummy channel structure 215 and the second gate electrode 350 (see, e.g., par. 0054).
Regarding Claim 20, Liaw teaches all aspects of claim 14. Liaw (see, e.g., Figs. 2-2, 3, 8-9), teaches that the conductive feature 409 is in contact with a top surface of the second gate electrode 350.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-7, 9, 14, and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin (US 2023/0260832).
Regarding Claim 1, Lin (see, e.g., Figs. 26A-26B), teaches a semiconductor device, comprising:
a first transistor (see, e.g., par. 0015), comprising:
a first gate structure 94 (see, e.g., par. 0012);
a first channel structure 160, overlapping with the first gate structure 94 (see, e.g., par. 0077);
a first source/drain feature 82 and a second source/drain feature 82, electrically connected with the first channel structure 160 (see, e.g., par. 0012);
a first source/drain contact 122 and a second source/drain contact 122, respectively electrically connected with the first source/drain feature 82 and the second source/drain feature 82 (see, e.g., par. 0048);
a second transistor (see, e.g., par. 0015), comprising:
a second gate structure 94 (see, e.g., par. 0012);
a second channel structure 160, overlapping with the second gate structure 94 (see, e.g., par. 0077); and
an interconnect structure 124/126/144, disposed over the first transistor and the second transistor (see, e.g., pars. 0055, 0072),
wherein the interconnect structure 124/126/144 comprises:
a first conductive via 144, electrically connecting the first source/drain contact 122 to the second gate structure 94, and in contact with a top surface of the first source/drain contact 122 and a side surface of the first source/drain contact 122 (see, e.g., par. 0072).
Regarding Claim 3, Lin teaches all aspects of claim 1. Lin (see, e.g., Figs. 26A-26B), teaches that the first source/drain contact 122 and the second source/drain contact 122 are embedded in an interlayer dielectric layer 88 disposed above the first source/drain feature 82 and the second source/drain feature 82, and the first conductive via 144 extends from a top surface of the interlayer dielectric layer 88 into the interlayer dielectric layer 88 (see, e.g., par. 0038).
Regarding Claim 4, Lin teaches all aspects of claim 3. Lin (see, e.g., Figs. 26A-26B), teaches that a portion of the second gate structure 94 is laterally located between a pair of gate spacers 80/86, an etching stop layer 87 is disposed on the gate spacers 80/86, and the interlayer dielectric layer 88 is disposed on the etching stop layer 87, wherein one of the pair of the gate spacers 80/86 is located underneath the first conductive via 144 (see, e.g., pars. 0029, 0031, 0038).
Regarding Claim 5, Lin teaches all aspects of claim 3. Lin (see, e.g., Figs. 26A-26B), teaches. wherein a portion of the second gate structure 94 is laterally located between a pair of gate spacers 80/86, an etching stop layer 87 is disposed on the gate spacers 80/86, and the interlayer dielectric layer 88 is disposed on the etching stop layer 87, wherein a portion of the first conductive via 144 is in contact with and located between one of the pair of the gate spacers 80/86 and the first source/drain contact 122.
Regarding Claim 6, Lin teaches all aspects of claim 3. Lin (see, e.g., Figs. 26A-26B), teaches. wherein the interlayer dielectric layer 88 is located above the first source/drain feature 82 and the second source/drain feature 82, and the first source/drain contact 122 and the second source/drain contact 122 are penetrating through the interlayer dielectric layer 88 and respectively electrically connected with the first source/drain feature 82 and the second source/drain feature 82.
Regarding Claim 7, Lin teaches all aspects of claim 3. Lin (see, e.g., Figs. 26A-26B), teaches that a top surface of the interlayer dielectric layer 88 is coplanar with the top surface of the first source/drain contact 122.
Regarding Claim 9, Lin teaches all aspects of claim 1. Lin (see, e.g., Figs. 26A-26B), teaches that the interconnect structure 124/126/144 comprises:
a first protective layer 124, disposed above the first source/drain contact 122 (see, e.g., par. 0055); and
a first insulation layer 126, disposed above the first protective layer 124, wherein the first conductive via 144 is penetrating through the first protective layer 124 and the first insulation layer 126 (see, e.g., par. 0055).
Regarding Claim 14, Lin (see, e.g., Figs. 26A-26B), teaches a semiconductor structure, comprising:
a first gate-all-around (GAA) structure 160 located between a first source/drain feature 82 and a second source/drain feature 82 (see, e.g., pars. 0012, 0077);
a first gate electrode 94 surrounding the first GAA structure 160 (see, e.g., par. 0012);
a first source/drain contact 122 and a second source/drain contact 122, respectively disposed above the first source/drain feature 82 and the second source/drain feature 82 (see, e.g., par. 0048);
a second gate electrode 94, wherein the first source/drain feature 82 is located between the first gate electrode 94 and the second gate electrode 94 (see, e.g., par. 0012);
a conductive feature 144 disposed above the first source/drain contact 122 and the second gate electrode 94, and the conductive feature 144 electrically connects the first source/drain contact 122 to the second gate electrode 94, wherein the conductive feature 144 is extending along a portion of a top surface of the first source/drain contact 122 and a portion of a side surface of the first source/drain contact 122 (see, e.g., par. 0072).
Regarding Claim 17, Lin teaches all aspects of claim 14. Lin (see, e.g., Figs. 26A-26B), teaches:
an interlayer dielectric layer 88, disposed above the first source/drain feature 82 and the second source/drain feature 82, and the first source/drain contact 122 and the second source/drain contact 122 are embedded in the interlayer dielectric layer 88 (see, e.g., par. 0038);
an etching stop layer 87, surrounding the interlayer dielectric layer 88 (see, e.g., par. 0038); and
gate spacers 80/86, disposed on the etching stop layer 87, wherein the conductive feature 144 is in contact with and located above one of the gate spacers 80/86 (see, e.g., pars. 0029, 0031).
Regarding Claim 18, Lin teaches all aspects of claim 17. Lin (see, e.g., Figs. 26A-26B), teaches that the one 80 of the gate spacers 80/86 is shorter than another one 86 of the gate spacers 80/86 located between the first gate electrode 94 and the first source/drain contact 122.
Regarding Claim 19, Lin teaches all aspects of claim 17. Lin (see, e.g., Figs. 26A-26B), teaches that the one of the gate spacers 80/86 comprises a thinner upper portion located between the conductive feature 144 and the second gate electrode 94 and a wider lower portion located underneath the conductive feature 144 (see, e.g., par. 0032).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 2022/0328499).
Regarding Claim 11, Liaw teaches all aspects of claim 10. Liaw does not show that a top surface of the source/drain contact 406 of the first pull-up GAA transistor W_PU-1 is coplanar with a top surface of the gate structure 240 of the second pull-down GAA transistor W_PD-2.
However, this claim limitation is merely considered a change in the height of the source/drain contact 406 and/or the gate structure 240 in Liaw’s device. The specific claimed top surface of the source/drain contact of the first pull-up transistor being coplanar with a top surface of the gate structure of the second pull-down transistor, absent any criticality, is only considered to be an obvious modification of the height of the source/drain contact 406 and/or the gate structure 240 in Liaw’s device, as the courts have held that changes in height without any criticality, are within the level of skill in the art. According to the courts, a particular height is nothing more than one among numerous heights that a person having ordinary skill in the art will find obvious to provide using routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of having the claimed top surface of the source/drain contact of the first pull-up transistor being coplanar with a top surface of the gate structure of the second pull-down transistor, it would have been obvious to one of ordinary skill in the art at the time of filing to have the claimed height in Liaw’s device.
CRITICALITY
The specification contains no disclosure of either the critical nature of having the claimed top surface of the source/drain contact of the first pull-up transistor being coplanar with a top surface of the gate structure of the second pull-down transistor or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen height or upon another variable recited in a claim, the applicant must show that the chosen height is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garcés whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nelson Garces/
Primary Examiner, Art Unit 2814