Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/ Restrictions
Applicant's election of group II without traverse: claims 1-14, in the “Response to Election / Restriction Filed - 12/30/2025”, cancellation of non-elected claim(s) 15-20 and submission of new claims 21-26 is/are acknowledged. This office action considers claims 1-14, 21-26, in “Claims - 12/30/2025”, pending for prosecution.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention;
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claim 8 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liaw et al. (US 20230033790 A1 - hereinafter Liaw).
Regarding Claim 8, Liaw teaches a semiconductor device (see the entire document; Figs. 51A-51D; specifically, [0041]-[0061], and as cited below), comprising:
a fin structure (218A, 218B – Fig. 51A-51D) disposed over a substrate (202) having a plurality of semiconductor layers (215 – Figs. 51A-51D – [0041]) vertically separated from one another (as shown in the figures);
a gate structure ({350B, 282}) that comprises a lower portion (282) and an upper portion (350B), wherein the lower portion wraps around each of the plurality of semiconductor layers of the fin structure (that is, 282 wraps around 215);
a plurality of intermediate layers (280) disposed between and separating the plurality of semiconductor layers (215) and the gate structure (282 – which is part of gate structure); and
inner spacers (255 – [0032]) vertically disposed between the plurality of semiconductor layers (215) and separating the lower portion of the gate structure (282) from source/drain structures (260 – [0034]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-4, 9-11, 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Miller et al. (US 20240387226 A1 - hereinafter Miller).
Regarding Claim 1, Liaw teaches a semiconductor device (see the entire document; Figs. 51A-51D; specifically, [0041]-[0061], and as cited below), comprising:
a plurality of semiconductor layers (215 – Figs. 51A-51D – [0041]) vertically separated from one another (as shown in the figures);
a gate structure ({350B, 282}) that comprises a lower portion (282) and an upper portion (350B), wherein the lower portion wraps around each of the plurality of semiconductor layers (that is, 282 wraps around 215); and
a plurality of diffusion cap layers (280) disposed between and separating the plurality of semiconductor layers (215) and the gate structure (282 – which is part of gate structure).
But Liaw does not expressly disclose the diffusion cap layers (280) function as diffusion barriers for the plurality of semiconductor layers. In [0041], Liaw teaches that 280 is formed of SiO.sub.2, HfSiO, SiON.
In a related art, Miller teaches in [0030] that “For example, silicon nitride, silicon oxide, or silicon oxynitride films may be used as diffusion barriers”.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to conclude that Liaw’s 280 is indeed diffusion barrier layer.
Regarding Claim 2, the combination of Liaw in view Miller teaches the semiconductor device of claim 1, wherein the plurality of diffusion cap layers each have a thickness of about 1 to 2 nanometers such that diffusion between the plurality of semiconductor layers is sufficiently impeded to prevent distortion of the plurality of semiconductor layers (Liaw – [0041]).
Regarding Claim 3, the combination of Liaw in view Miller teaches the semiconductor device of claim 1, wherein the plurality of semiconductor layers include silicon (Liaw – [0020]).
Regarding Claim 4, the combination of Liaw in view Miller teaches the semiconductor device of claim 1, wherein the plurality of diffusion cap layers include silicon nitride (Liaw – [0041]).
Regarding claim 9, Liaw teaches claim 8 from which claim 9 depends. But Liaw does not expressly disclose wherein the plurality of intermediate layers function as diffusion barriers for the plurality of semiconductor layers. In [0041], Liaw teaches that 280 is formed of SiO.sub.2, HfSiO, SiON.
In a related art, Miller teaches in [0030] that “For example, silicon nitride, silicon oxide, or silicon oxynitride films may be used as diffusion barriers”.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to conclude that Liaw’s 280 is indeed diffusion barrier layer.
Regarding Claim 10, the combination of Liaw in view Miller teaches the semiconductor device of claim 8, wherein the plurality of intermediate layers each have a thickness of about 1 to 2 nanometers such that diffusion between the plurality of semiconductor layers is sufficiently impeded to prevent distortion of the plurality of semiconductor layers (Liaw – [0041]).
Regarding Claim 11, the combination of Liaw in view Miller teaches the semiconductor device of claim 8, wherein the plurality of semiconductor layers include silicon and the plurality of intermediate layers include silicon nitride (Liaw – [0041]).
Regarding Claim 21, Liaw teaches a semiconductor device (see the entire document; Figs. 51A-51D; specifically, [0041]-[0061], and as cited below), comprising:
a fin structure (218A, 218B – Fig. 51A-51D) on a substrate (202) that extends along a first lateral direction of the substrate (202), wherein the fin structure includes a plurality of semiconductor layers (215) vertically separated from one another (seen in the figures);
an active gate structure (282) that wraps around each of the semiconductor layers (215) of the fin structure by filling spaces therebetween (see the figures);
diffusion cap layers (280) between and separating the active gate structure (282) and the semiconductor layers (215);
gate spacers (247) lining sidewalls of the active gate structure (282),
etch stop layers (CESL – [0036]) between and separating the gate spacers (247) and the fin structure (218); and
source/drain structures (260A, 260B – [0036]) that are respectively coupled to ends of the fin structure (218).
But Liaw does not expressly disclose wherein the diffusion cap layers function as diffusion barriers.
In [0041], Liaw teaches that 280 is formed of SiO.sub.2, HfSiO, SiON.
In a related art, Miller teaches in [0030] that “For example, silicon nitride, silicon oxide, or silicon oxynitride films may be used as diffusion barriers”.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to conclude that Liaw’s 280 is indeed diffusion barrier layer.
Regarding Claim 22, the combination of Liaw in view Miller teaches the semiconductor device of claim 21, wherein the diffusion cap layers each have a thickness of about 1 to 2 nanometers such that diffusion between the plurality of semiconductor layers is sufficiently impeded to prevent distortion of the plurality of semiconductor layers (Liaw – [0041]).
Regarding Claim 23, the combination of Liaw in view Miller teaches the semiconductor device of claim 21, wherein the semiconductor layers include silicon (Liaw – [0020]), and the diffusion cap layers (280) reduce diffusion of germanium from other layers of the fin structure to the semiconductor layers (since Miller teaches 280 acts as diffusion barrier layers).
Regarding Claim 24, the combination of Liaw in view Miller teaches the semiconductor device of claim 21, wherein the diffusion cap layers include silicon nitride (Liaw – [0041]).
Allowable Subject Matter
Claims 5-7, 12-14, 25-26 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner’s Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 5: The semiconductor device of claim 1, wherein the plurality of semiconductor layers extend between and electrically couple source/drain structures along a first direction, regions of the lower portion of the gate structure are disposed between the plurality of semiconductor layers and the source/drain structures, wherein the plurality of semiconductor layers each have heights normal to the first direction of about 8 to 9 nanometers, and the regions of the lower portion of the gate structure each have heights normal to the first direction of about 6 to 7 nanometers.
Regarding claim 6: The semiconductor device of claim 1, wherein the plurality of semiconductor layers extend between and electrically couple source/drain structures along a first direction, regions of the lower portion of the gate structure are disposed between the plurality of semiconductor layers and the source/drain structures, and the regions of the lower portion of the gate structure have cross-sectional shapes along the first direction having inner corner angles of about 90 to 105 degrees.
Regarding claim 7: The semiconductor device of claim 1, further comprising inner spacers vertically disposed between the plurality of semiconductor layers and separating the lower portion of the gate structure from source/drain structures, wherein first surfaces of the lower portion of the gate structure and first surfaces of the inner spacers define an angle therebetween of about 165 to 180 degrees, wherein the first surfaces of the lower portion of the gate structure and the first surfaces of the inner spacers are both in contact with the plurality of diffusion cap layers.
Regarding claim 12: The semiconductor device of claim 8, wherein the plurality of semiconductor layers extend between and electrically couple the source/drain structures along a first direction, regions of the lower portion of the gate structure are disposed between the plurality of semiconductor layers and the source/drain structures, wherein the plurality of semiconductor layers each have heights normal to the first direction of about 8 to 9 nanometers, and the regions of the lower portion of the gate structure each have heights normal to the first direction of about 6 to 7 nanometers.
Regarding claim 13: The semiconductor device of claim 8, wherein the plurality of semiconductor layers extend between and electrically couple the source/drain structures along a first direction, regions of the lower portion of the gate structure are disposed between the plurality of semiconductor layers and the source/drain structures, and the regions of the lower portion of the gate structure have cross-sectional shapes along the first direction having inner corner angles of about 90 to 105 degrees.
Regarding claim 14: The semiconductor device of claim 8, wherein first surfaces of the lower portion of the gate structure and first surfaces of the inner spacers define an angle therebetween of about 165 to 180 degrees, wherein the first surfaces of the lower portion of the gate structure and the first surfaces of the inner spacers are both in contact with the plurality of intermediate layers.
Regarding claim 25: The semiconductor device of claim 21, wherein the semiconductor layers extend between and electrically couple the source/drain structures along a first direction, regions of the active gate structure are disposed between the semiconductor layers and the source/drain structures, wherein the semiconductor layers each have heights normal to the first direction of about 8 to 9 nanometers, and the regions of the active gate structure each have heights normal to the first direction of about 6 to 7 nanometers.
Regarding claim 26: The semiconductor device of claim 21, further comprising inner spacers vertically disposed between the semiconductor layers and separating the active gate structure from source/drain structures, wherein first surfaces of the active gate structure and first surfaces of the inner spacers define an angle therebetween of about 165 to 180 degrees, wherein the first surfaces of the active gate structure and the first surfaces of the inner spacers are both in contact with the diffusion cap layers.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898