Attorney Docket Number: 2515.0632
Filing Date: 9/01/2023
Inventors: Shin et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the amendments filed 1/12/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the
first inventor to file provisions of the AIA . In the event the determination of the status of the
application as to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis
(i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of
rejection if the prior art relied upon, and the rationale supporting the rejection, would be the
same under either status.
Acknowledgement
The Amendment filed on 1/12/2026, responding to the Office action mailed 12/22/2025, has been entered. Applicant amended claims 1, 3, 7, 26, and 32, and cancelled claim 9. The present Office action is made with all the suggested amendments being fully considered.
Response to Amendments
Applicant’s amendments to the claims have overcome the respective claim rejections
under Non-statutory double patenting and 35 U.S.C. 103 as previously formulated in the Non-Final Office action mailed on 12/22/2025. Accordingly, the claim rejections of NSDP double patenting and 35 U.S.C. 103 are hereby withdrawn. Accordingly, pending in this application are claims 1-8, 10-13, and 26-37. New grounds of rejections are presented below, however, as necessitated by applicant’s amendments to the claims.
Claim Interpretation
Claims 3, 10, 28, and 34 recite the line “…etching an RDL pattern into the first insulating layer…”, which will be interpreted as “…forming an RDL pattern into an etched portion of the first insulating layer…”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 8361842 B2) in view of Chen (WO 2018152907 A1) further in view of Chang (US 20210384142 A1).
Regarding claim 32, Yu (see, e.g., fig. 6) shows most aspects of the instant invention including a method of making a semiconductor device comprising:
Providing an electrical component (e.g., interconnect structure comprising bond pads 22 and integrated circuit devices 23);
Depositing an encapsulant (e.g., molding compound 34) over the electrical component (e.g., interconnect structure comprising bond pads 22 and integrated circuit devices 23);
Forming (see, e.g., paragraph 15 “…formation of metal bumps…”) a conductive layer (e.g., layer built up of metal bumps 42) over the encapsulant (e.g., molding compound 34), wherein the conductive layer (e.g., layer built up of metal bumps 42) includes a plurality of metal balls (e.g., metal bumps 42);
Yu (see, e.g., fig. 4), however, fails to show wherein these metal-balls are graphene coated, and wherein the plurality of these graphene-coated metal balls is embedded in a matrix.
Chen (see, e.g., fig. 1), in a similar device to Yu, teaches a metal ball (e.g., metal bump 10) is graphene-coated (see, e.g., graphene layer 12).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the graphene-coat of Chen onto the metal balls of Yu, in order to increase the conductivity and performance of the metal, as taught by Chen (see paragraph text).
Yu in view of Chen, however, fails to explicitly teach the plurality of graphene-coated metal balls embedded in a matrix.
Chang (see, e.g.., fig. 1), in a similar device to Yu in view of Chen, teaches a plurality of solder balls (e.g., solder balls SB) are embedded in a matrix (see, e.g., paragraph 3 “The solder balls are set on a package surface in a matrix array which can provide more signal contacts”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the matrix array configuration of Chang within the graphene-coated metal ball arrangement of Yu in view of Chen in order to increase the density and performance of the ball array within the device as necessary.
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Chen further in view of Chang and Chu (US 20170221819 A1).
Regarding claim 33, Yu in view of Chen further in view of Chang fails to teach disposing a mask over the encapsulant.
Chu (see, e.g., fig. 7), in a similar device to Yu in view of Chen further in view of Chang, teaches disposing a mask (see, e.g., paragraph 31 “forming and patterning a mask layer…”) over an encapsulant (e.g., encapsulation material 52).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the mask disposal of Chu within the method process of Yu in view of Chen further in view of Chang, in order to protect the encapsulant/redistribution structure for future etching/plating as necessary.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of You (US 20210193686 A1) further in view of Chen and Chang.
Regarding claim 7, Yu (see, e.g., fig. 6) shows most aspects of the instant invention including a method of making a semiconductor device comprising:
providing an electrical component (e.g., interconnect structure comprising bond pads 22 and integrated circuit devices 23) over the carrier (e.g., carrier 30);
Depositing an encapsulant (e.g., molding compound 34) over the electrical component (e.g., interconnect structure comprising bond pads 22 and integrated circuit devices 23);
Forming (see, e.g., paragraph 15 “…formation of metal bumps…”) a conductive layer (e.g., layer built up of metal bumps 42) over the encapsulant (e.g., molding compound 34), wherein the conductive layer (e.g., layer built up of metal bumps 42) includes a plurality of metal balls (e.g., metal bumps 42);
Yu (see, e.g., fig. 6), however, fails to show sintering the conductive layer by intensive pulsed light (IPL) irradiation, while it also fails to show wherein the conductive layer is deposited as a plurality of graphene-coated metal balls embedded in a matrix.
You (see, e.g., fig. 12), in a similar device to Yu, teaches sintering a conductive layer (e.g., conductive layer portion CP) by intensive pulsed light (IPL) irradiation (see, e.g., paragraph 70 “…high energy IPL is irradiated again to the conductive pattern CP to sinter the transferred conductive layer portion CP′ to provide the conductive pattern with high strength and high adhesion to the substrate”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the IPL sintering of You onto the conductive layer of Yu, in order to provide additional strength within the conductive layer, as taught by You (see paragraph 70).
Chen (see, e.g., fig. 1), in a similar device to Yu in view of You, teaches a metal ball (e.g., metal bump 10) is graphene-coated (see, e.g., graphene layer 12).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the graphene-coat of Chen onto the metal balls of Yu in view of You, in order to increase the conductivity and performance of the metal, as taught by Chen (see paragraph text).
Yu in view of You further in view of Chen, however, fails to explicitly teach the plurality of graphene-coated metal balls embedded in a matrix.
Chang (see, e.g.., fig. 1), in a similar device to Yu in view of You further in view of Chen, teaches a plurality of solder balls (e.g., solder balls SB) are embedded in a matrix (see, e.g., paragraph 3 “The solder balls are set on a package surface in a matrix array which can provide more signal contacts”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the matrix array configuration of Chang within the graphene-coated metal ball arrangement of Yu in view of You further in view of Chen in order to increase the density and performance of the ball array within the device as necessary.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of You further in view of Chen, Chang, and Chu.
Regarding claim 8, Yu in view of You further in view of Chen and Chang fails to teach disposing a mask over the encapsulant during sintering.
Chu (see, e.g., fig. 7), in a similar device to Yu in view of You further in view of Chen and Chang, teaches disposing a mask (see, e.g., paragraph 31 “forming and patterning a mask layer…”) over an encapsulant (e.g., encapsulation material 52).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the mask disposal of Chu within the method process of Yu in view of You further in view of Chen and Chang during sintering, in order to protect the RDL/encapsulant from the conductive layer’s sintering process.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of You further in view of Chen, Chang, and Lin (US 20150155248 A1).
Regarding claim 10, Yu (see, e.g., figs. 5-6) shows forming a first insulating layer (e.g., dielectric layer 38) over the encapsulant (e.g., molding compound 34), forming an RDL pattern (see, e.g., paragraph 14 “redistribution layer(s) (RDL) are formed……conductive traces 40”) into the first insulating layer (e.g., dielectric layer 38), and forming the conductive layer (e.g., layer built up of metal bumps 42).
Yu in view of You further in view of Chen and Chang, however, fails to explicitly teach the RDL pattern is formed in an etched portion of the first insulating layer.
Lin (see, e.g., fig. 3), in a similar device to Yu in view of You further in view of Chen and Chang, teaches forming an RDL pattern (e.g., RDL 174) into an etched portion (see, e.g., paragraph 56 “A portion of insulating layer 176 is removed by an etching process to expose RDL 174”) of a first insulating layer (e.g., insulating layer 176).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the etching step of Lin within the method process of Yu in view You further in view of Chen and Chang, in order to achieve the expected result of providing openings within the insulating layer for electrical contact between the conductive layer and the RDL pattern, as necessary.
Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Chen further in view of Chang and Lin (US 20170221819 A1).
Regarding claim 34, Yu (see, e.g., figs. 5-6) shows forming a first insulating layer (e.g., dielectric layer 38) over the encapsulant (e.g., molding compound 34), forming an RDL pattern (see, e.g., paragraph 14 “redistribution layer(s) (RDL) are formed……conductive traces 40”) into the first insulating layer (e.g., dielectric layer 38), and forming the conductive layer (e.g., layer built up of metal bumps 42).
Yu in view of Chen further in view of Chang, however, fails to explicitly teach the RDL pattern is formed in an etched portion of the first insulating layer.
Lin (see, e.g., fig. 3), in a similar device to Yu in view of Chen further in view of Chang, teaches forming an RDL pattern (e.g., RDL 174) into an etched portion (see, e.g., paragraph 56 “A portion of insulating layer 176 is removed by an etching process to expose RDL 174”) of a first insulating layer (e.g., insulating layer 176).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the etching step of Lin within the method process of Yu in view of Chen further in view of Chang, in order to achieve the expected result of providing openings within the insulating layer for electrical contact between the conductive layer and the RDL pattern, as necessary.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of You further in view of Chen, Chang, Lin and Hsu.
Regarding claim 11, Yu in view of You further in view of Chen, Chang, and Lin fails to teach forming a second insulating layer over the conductive layer; forming an opening through the second insulating layer to expose the conductive layer, and forming a solder bump in the opening on the conductive layer.
Hsu (see, e.g., fig. 1D), in a similar device to Yu in view of You further in view of Chen, Chang, and Lin, teaches forming an insulating layer (e.g., insulating protection layer 25) over (e.g., flip orientation of fig. 1D) the conductive layer (e.g., metal bumps 26), forming an opening (e.g., openings of insulating protection layer 25) through the insulating layer (e.g., insulating protection layer 25) to expose the conductive layer (e.g., metal bumps 26), and forming a solder bump (e.g., solder bump 30) in the opening on the conductive layer (e.g., metal bumps 26).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the additional insulating layer and solder bump of Hsu on top of the conductive layer of Yu in view of You further in view Chen, Chang, and Lin, in order to achieve the expected result of extending the connectivity interface for additional conductivity requirements as necessary.
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Chen further in view of Chang, Lin, and Hsu.
Regarding claim 35, Yu in view of Chen further in view of Chang and Lin fails to teach forming a second insulating layer over the conductive layer; forming an opening through the second insulating layer to expose the conductive layer, and forming a solder bump in the opening on the conductive layer.
Hsu (see, e.g., fig. 1D), in a similar device to Yu in view of Chen further in view of Chang and Lin, teaches forming an insulating layer (e.g., insulating protection layer 25) over (e.g., flip orientation of fig. 1D) the conductive layer (e.g., metal bumps 26), forming an opening (e.g., openings of insulating protection layer 25) through the insulating layer (e.g., insulating protection layer 25) to expose the conductive layer (e.g., metal bumps 26), and forming a solder bump (e.g., solder bump 30) in the opening on the conductive layer (e.g., metal bumps 26).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the additional insulating layer and solder bump of Hsu on top of the conductive layer of Yu in view of Chen further in view of Chang and Lin, in order to achieve the expected result of extending the connectivity interface for additional conductivity requirements as necessary.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of You, Chen, Chang, Lin, and Fang (US 20140124950 A1).
Regarding claim 12, Yu in view of You further in view of Chen, Chang, and Lin fails to teach forming a second insulating layer between the encapsulant and first insulating layer, forming a via in the second insulating layer, and forming the RDL pattern over the via.
Fang (see, e.g., fig. 2D/2E), in a similar device to Yu in view of You further in view of Chen, Chang, and Lin, teaches forming a second insulating layer (e.g., dielectric layer 240) adjacent to a first insulating layer (see, e.g., insulating layer 25), forming a via (e.g., conductive via 242) in the second insulating layer (e.g., dielectric layer 240).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the second insulating layer and via of Fang between the encapsulant and first insulating layer of Yu in view of You further in view of Chen, Chang, and Lin, in order to extend the electrical connectivity interface while also maintaining electrical connectivity between the alternate layers. Note that the RDL pattern was formed in the upper first insulating layer, which is arranged over the via in the intermediate second insulating layer.
Regarding claim 13, Yu in view of You further in view of Chen, Chang, and Lin fails to teach forming a via in the first insulating layer in the first insulating layer under the RDL pattern.
Fang (see, e.g., fig. 2D), in a similar device to Yu in view of You further in view of Chen, Chang, and Lin, teaches forming a via (e.g., conductive via 242) in a first insulating layer (e.g., dielectric layer 240) within an RDL pattern (e.g., RDL structure 24).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to form the via of Fang within the first insulating layer of Yu in view of You further in view of Chen, Chang, and Lin, in order to achieve the expected result of providing electrical connectivity between the alternate layers of the device.
Claims 36-37 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Chen further in view of Chang, Lin, and Fang.
Regarding claim 36, Yu in view of Chen further in view of Chang and Lin fails to teach forming a second insulating layer between the encapsulant and first insulating layer, forming a via in the second insulating layer, and forming the RDL pattern over the via.
Fang (see, e.g., fig. 2D/2E), in a similar device to Yu in view of Chen further in view of Chang and Lin, teaches forming a second insulating layer (e.g., dielectric layer 240) adjacent to a first insulating layer (see, e.g., insulating layer 25), forming a via (e.g., conductive via 242) in the second insulating layer (e.g., dielectric layer 240).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the second insulating layer and via of Fang between the encapsulant and first insulating layer of Yu in view of Chen further in view of Chang and Lin, in order to extend the electrical connectivity interface while also maintaining electrical connectivity between the alternate layers. Note that the RDL pattern was formed in the upper first insulating layer, which is arranged over the via in the intermediate second insulating layer.
Regarding claim 37, Yu in view of Chen further in view of Chang and Lin fails to teach forming a via in the first insulating layer in the first insulating layer under the RDL pattern.
Fang (see, e.g., fig. 2D), in a similar device to Yu in view of Chen further in view of Chang and Lin, teaches forming a via (e.g., conductive via 242) in a first insulating layer (e.g., dielectric layer 240) within an RDL pattern (e.g., RDL structure 24).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to form the via of Fang within the first insulating layer of Yu in view of Chen further in view of Chang and Lin, in order to achieve the expected result of providing electrical connectivity between the alternate layers of the device.
Allowable Subject Matter
Claims 1-6 and 26-31 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 1, the closest identified prior art, Yu (US 8361842 B2) in view of Chen (WO 2018152907 A1) further in view of You (US 20210193686 A1) and Chang (US 20210384142 A1) teaches most aspects of the method of making a semiconductor device.
However, Yu in view of Chen further in view of You and Chang fails to disclose or suggest wherein the electrical component includes a plurality of conductive pillars oriented away from the carrier, wherein the conductive layer extends continuously across an entire width of the electrical component, wherein the encapsulant extends to physically contact side surfaces of each of the conductive pillars, wherein the conductive layer extends continuously across an entire width of the electrical component and physically contacts each of the conductive pillars, and wherein the graphene-coated metal balls are each interconnected as one graphene-coated metal ball of the plurality of graphene-coated metal balls physically contacts another graphene-coated metal ball of the plurality of graphene- coated metal balls within the conductive layer to form a continuous conduction path through the graphene-coated metal balls between the conductive pillars; and backgrinding the conductive layer to leave a redistribution layer (RDL) pattern after sintering.
Therefore, the above limitations in the entirety of the claim are neither anticipated nor rendered obvious over the prior art of record.
Regarding claim 26, the closest identified prior art, Yu (US 8361842 B2) in view of Chen (WO 2018152907 A1) further in view of You (US 20210193686 A1, Lee, (US 20240128230 A1), and Chang (US 20210384142 A1) teaches most aspects of the method of making a semiconductor device.
However, Yu in view of Chen further in view of You, Lee, and Chang fails to disclose or suggest wherein the conductive layer extends continuously across an entire width of the electrical component, and wherein the graphene-coated metal balls are each interconnected as one graphene-coated metal ball of the plurality of graphene-coated metal balls physically contacts another graphene-coated metal ball of the plurality of graphene-coated metal balls within the conductive layer to form a continuous conduction path through the conductive layer.
Therefore, the above limitations in the entirety of the claim are neither anticipated nor rendered obvious over the prior art of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee, and, to avoid processing delays, should preferably accompany the issue fee. Such admissions should be clearly labeled “Comments on Statement of Reasons for Allowance”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner
should be directed to Thomas McCoy at (571) 272-0282 and between the hours of 9:30 AM to 6:30 PM
(Eastern Standard Time) Monday through Friday or by e-mail via Thomas.McCoy@uspto.gov. If attempts
to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814