Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the election filed on 04/20/2026. Applicant elected Group II, Species (i), without traverse. Currently, claims 2-13 and 15-20 are pending.
Claim Objections
Claim 17 is objected to because of the following informalities:
In claim 17, line 3, the recitation “patterns” appears to be “platens”.
Appropriate correction is required.
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-7, 13, 15-16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (Pub. No. US 2016/0141249 A1, herein Kang) in view of Lu et al. (Pub. No. US 2025/0015027 A1, herein Lu).
Regarding claim 7, Kang discloses a method of forming a semiconductor device, the method comprising: forming a first structure (Fig. 3), wherein forming the first structure comprises: forming a first metal layer 120 ([0045]) over a first substrate 100 ([0044]); forming a first dielectric layer 130 ([0046]) over the first metal layer; forming a dielectric film 140-150-160 ([0044]) over the first dielectric layer, wherein the dielectric film is comprised of a first dielectric ([0061], [0089]); etching a trench 165 ([0076]) in the dielectric film and first dielectric layer, wherein the trench extends from a top surface of the dielectric film down to at least a top surface of the first metal layer (Fig. 4); and filling the trench with a first copper-containing material 180 ([0081]); contacting the first structure with a second structure (Fig. 10), the second structure comprising: a second metal layer 220 ([0045]) overlaying a second substrate 200 ([0047]); a second dielectric layer 230-240-260 ([0046]) overlaying the second metal layer and defining a second set of one or more features 290 ([0044]) in the second dielectric layer, wherein the second dielectric layer is comprised of a second dielectric ([0074]), and a second copper-containing material 282 ([0050]) deposited within the second set of one or more features; and bonding the first structure to the second structure (Fig. 10 and [0098]), wherein the first copper-containing material of the first structure contacts the second copper-containing material of the second structure ([0100]).
Kang does not specifically show wherein the second dielectric is a different material than the first dielectric; and wherein the dielectric film of the first structure is hybrid bonded to the second dielectric layer of the second structure.
However, in the same field of endeavor, Lu teaches a hybrid boding method in semiconductor packages ([0005], [0020]), wherein the second dielectric is a different material than the first dielectric; and wherein the dielectric film of the first structure is hybrid bonded to the second dielectric layer of the second structure ([0030]; “In some embodiments, second dielectric layer 124 can include a dielectric material the same as or different from first dielectric layer 120.”) which provides top and bottom hybrid bonding structures in IC die packages with stronger bonds, better manufacturing process control, and reduced susceptibility to delamination, and methods of forming the top and bottom hybrid bonding structures with shorter planarization process times and lower bonding process temperatures ([0021]-[0022]).
Therefore, given the teachings of Lu, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Kang in view of Lu by employing the second dielectric with different material than the first dielectric.
Regarding claim 2, Kang in view of Lu teaches the method of claim 7, wherein the first dielectric layer is comprised of the second dielectric (Kang: [0046], [0057]).
Regarding claim 3, Kang in view of Lu teaches the method of claim 7, wherein the first dielectric comprises silicon carbon nitride and wherein the second dielectric comprises silicon oxide (Kang: [0046], [0057]). See In re Leshin, 277 F.2d 197, 199 (CCPA 1960); the selection of a known material based upon its suitability for the intended use is a design consideration within the skill of the art.
Regarding claim 4, Kang in view of Lu teaches the method of claim 7, wherein the first dielectric comprises silicon oxynitride and wherein the second dielectric comprises silicon oxide (Kang: [0046], [0057]). See In re Leshin, 277 F.2d 197, 199 (CCPA 1960); the selection of a known material based upon its suitability for the intended use is a design consideration within the skill of the art.
Regarding claims 5 and 6, Kang in view of Lu teaches thin layers, wherein the first copper-containing material is characterized by a dish profile (Fig. 10). Kang in view of Lu does not specifically state the dielectric film has a thickness of 5 nm and the first copper-containing material has a dish depth of less than or about 1 nm. However, the claimed thickness range is recognized as a result-effective variable, i.e., a variable which achieves a recognized result. If the dielectric is too thick, metal pads may not touch well, if the dielectric is too thin, metal protrudes too much. Different dielectric thicknesses change mechanical stiffness; a thicker dielectric can absorb thermal stress but also increase warpage, it may reduce stress concentration near metal edges but also create mismatch in deformation between two substrates. Dielectric thickness also affects the spacing between conductive features; thinner dielectric layers cause higher parasitic capacitance whereas thicker dielectric layers lower capacitance. Furthermore, very thin dielectric layers in this configuration lower via/interconnect height, lower series resistance and provide faster signal transmission. Therefore, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose the particular claimed thickness range because applicant has not disclosed that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another range. The claim(s) is(are) obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. See In re Aller, 105 USPQ 233 (CCPA 1955) and In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art).
Regarding claim 13, Kang in view of Lu teaches the method of claim 7, further comprising forming a liner 122 (Kang: [0051]) in the trench, and wherein filling the trench with the first copper-containing material comprises overlaying the liner with the first copper-containing material (Kang: [0052]).
Regarding claim 15, Kang in view of Lu teaches the method of claim 7, wherein the first dielectric comprises silicon oxide and wherein the second dielectric comprises silicon oxynitride (Kang: [0046], [0057]). See In re Leshin, 277 F.2d 197, 199 (CCPA 1960); the selection of a known material based upon its suitability for the intended use is a design consideration within the skill of the art.
Regarding claim 16, Kang in view of Lu teaches the method of claim 7, wherein the first dielectric comprises silicon oxide and wherein the second dielectric comprises silicon carbon nitride (Kang: [0046], [0057]). See In re Leshin, 277 F.2d 197, 199 (CCPA 1960); the selection of a known material based upon its suitability for the intended use is a design consideration within the skill of the art.
Regarding claim 18, Kang in view of Lu teaches the method of claim 7, wherein the first dielectric layer is comprised of a third dielectric, wherein the third dielectric is a different material than the first dielectric and the second dielectric (Kang: [0046], [0057]).
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Lu, as applied above, and further in view of Yu et al. (Pub. No. US 2013/0330906 A1, herein Yu).
Regarding claims 8 and 9, the previous combination does not specifically explain etching the trench in the dielectric film with a chlorine-based etch or etching the trench in the dielectric film and first dielectric layer with a multi-material etch, wherein the multi-material etch comprises two or more of: a chlorine-based etch, a fluorine-based etch, an oxygen-plasma etch, and a fluorine-and- oxygen-based etch.
However, in the same field of endeavor, Yu teaches a method of semiconductor integrated circuit fabrication, comprising: wherein etching the trench 230 (Yu: [0011]) in the dielectric film and first dielectric layer comprises etching the trench in the dielectric film with a chlorine-based etch (Yu: [0012]), or wherein etching the trench in the dielectric film and first dielectric layer comprises etching the trench in the dielectric film and first dielectric layer with a multi-material etch, wherein the multi-material etch comprises two or more of: a chlorine-based etch, a fluorine-based etch, an oxygen-plasma etch, and a fluorine-and- oxygen-based etch (Yu: [0012]) to gain etch selectivity, flexibility and desired etch profile (Yu: [0012]).
Therefore, given the teachings of Yu, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying the previous combination in view of Yu by employing the multi-material etch process.
Regarding claim 10, Kang in view of Lu and further in view of Yu teaches the method of claim 7, wherein forming the first metal layer and forming the first dielectric layer is performed in a first chamber (Yu: [0013]), wherein etching the trench in the dielectric film and the first dielectric layer is performed in a second chamber, wherein the first structure is moved from the first chamber to the second chamber without exposing the first substrate to an external atmosphere (Yu: [0021], Transferring the substrate between deposition and etch chambers under vacuum, without exposure to ambient atmosphere, preserves surface cleanliness, suppresses native oxide formation, and enables formation of abrupt, low-defect interfaces with improved process uniformity and device performance.).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Lu, as applied above, and further in view of Fountain et al. (Pub. No. US 2019/0096842 A1, herein Fountain).
Regarding claim 11, the previous combination does not specifically state further comprising contacting the first structure with one or more slurries and one or more platens, wherein the one or more slurries and one or more platens removes a portion of the first copper-containing material and a second portion of the dielectric film.
However, in the same field of endeavor, Fountain teaches a method of chemical mechanical polishing for hybrid bonding, comprising: contacting the first structure with one or more slurries and one or more platens, wherein the one or more slurries and one or more platens removes a portion of the first copper-containing material and a second portion of the dielectric film (Fountain: [0026], [0070]) to improve the planarization of the surface and the conductive structure dishing, which in turn, would improve the yield and reliability of the hybrid bonding technique ([0005]-[0006]).
Therefore, given the teachings of Fountain, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying the previous combination in view of Fountain by employing the polishing method of Fountain.
Allowable Subject Matter
Claims 12, 17 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 12, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein contacting the first structure with the one or more slurries and one or more platens recesses the first copper-containing material a distance of less than or about 1 nm within the trench below a top surface of the dielectric film.
With respect to claim 17, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, further comprising contacting the first structure with one or more slurries and one or more platens, wherein the one or more slurries and one or more platens remove a portion of the first copper-containing material and a second portion of the first dielectric layer, wherein contacting the first structure with the one or more slurries recesses the first dielectric layer a distance of greater than or about 5 nm from a top surface of the first copper-containing material.
With respect to claim 19, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein selectively depositing the dielectric film on the first structure comprises: depositing a polymer on the first structure, wherein the polymer forms a monolayer on the first copper-containing material, wherein the polymer does not form the monolayer on the first dielectric layer; depositing a dielectric material on the first structure via atomic layer deposition, wherein the dielectric material forms the dielectric film on the first dielectric layer, wherein the dielectric film does not form on the first copper-containing material; and removing the monolayer. Claim 20 is included likewise as it depends from claim 19.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
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May 16, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813
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