Prosecution Insights
Last updated: April 19, 2026
Application No. 18/460,578

INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF

Non-Final OA §103
Filed
Sep 03, 2023
Examiner
ENAD, CHRISTINE A
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
To Grant
94%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
1105 granted / 1312 resolved
+16.2% vs TC avg
Moderate +10% lift
Without
With
+10.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
68 currently pending
Career history
1380
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
61.5%
+21.5% vs TC avg
§102
21.1%
-18.9% vs TC avg
§112
7.7%
-32.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1312 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I in the reply filed on 12/22/2025 is acknowledged. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-6, 21-26 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US Publication No. 2016/0020210) in view of Liaw (US Publication No. 2020/0105616). Regarding claim 1, Liaw 210 discloses an integrated circuit, comprising: an active structure Fig 5A, 106/108, formed on a semiconductor substrate Fig 5B, 202, and extending along a first lateral direction Fig 5A; first and second gate lines Fig 5A, 110/112/114/115, extending along a second lateral direction on the semiconductor substrate Fig 5B, 202, and crossing the active structure Fig 5A-5B; an isolation wall Fig 5A, 224, extending along the second lateral direction between the first and second gate lines Fig 5A, and cutting through the active structure Fig 5A; a first source/drain contact Fig 5A, 120/121/122/123/124/125/126/127, extending along the second lateral direction between the first gate line and the isolation wall Fig 5A, and crossing the active structure Fig 5A. Liaw 210 discloses all the limitations but is silent on the source drain contact arrangement. Whereas Liaw 616 discloses a first source/drain via Fig 40B or 40C, 242, disposed on the first source/drain contact Fig 40B, 142/145, and laterally extending along the first direction to overlap the isolation wall Fig 40C, 312 ¶0027 also Fig 39-42. Liaw 210 and Liaw 616 are analogous art because they are directed to semiconductor devices having isolation structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify Liaw 210 because they are from the same field of endeavor. Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the contact/via arrangement and incorporate the teachings of Liaw 616 to improve interconnection. Regarding claim 2, Liaw 210 discloses a second source/drain contact Fig 5A-5B, 120/121/122/123/124/125/126/127, extending along the second lateral direction between the second gate line Fig 5A, 110/112/114/115 and the isolation wall Fig 5A, 224, and crossing the active structure Fig 5A, 106/108; While Liaw 616 discloses a second source/drain via, disposed on the second source/drain contact, and laterally extending along the first direction to overlap the isolation wall Fig 39-42. Regarding claim 3, Liaw 616 discloses wherein the first and second source/drain vias are spaced apart from each other along the second lateral direction Fig 38 ¶0027. Regarding claim 4, Liaw 616 discloses, wherein the first and second source/drain vias at most extend to a central line of the isolation wall from opposite sides of the isolation wall Fig 40C. Regarding claim 5, Liaw 210 discloses a second source/drain contact Fig 5A-5B, 120/121/122/123/124/125/126/127, extending along the second lateral direction between the second gate line Fig 5A, 110/112/114/115 and the isolation wall Fig 5A, 224, and crossing the active structure Fig 5A, 106/108; While Liaw 616 discloses wherein the first source/drain via extends across the isolation wall from above and establish contact with both of the first and second source/drain contacts Fig 39-42. Regarding claim 6, Liaw 210 discloses a second source/drain contact Fig 5A-5B, 120/121/122/123/124/125/126/127, extending along the second lateral direction between the second gate line Fig 5A, 110/112/114/115 and the isolation wall Fig 5A, 224, and crossing the active structure Fig 5A, 106/108; While Liaw 616 discloses a second source/drain via Fig 38, disposed on the second source/drain contact Fig 38, wherein the second source/drain via is laterally spaced apart from the isolation wall Fig 39-42. Regarding claim 21, Liaw 210 discloses an integrated circuit, comprising: an active structure Fig 5A, 106/108, formed on a semiconductor substrate Fig 5B, 202, and extending along a first direction Fig 5A; a first source/drain contact Fig 5A, 120/121/122/123/124/125/126/127, disposed on a first epitaxial structure¶0026, extending along a second direction perpendicular to the first direction Fig 5A-5B, and crossing the active structure Fig 5A-5B; a first gate line Fig 5A, 110/112/114/115, extending along the second direction on the semiconductor substrate Fig 5A-5B, disposed at a first side of the first source/drain contact Fig 5A, and crossing the active structure; an isolation wall, extending along the second direction Fig 5A-5B, disposed at a second side of the first source/drain contact Fig 5A-5B, and cutting through the active structure Fig 5A-5B, wherein the second side is opposite to the first side Fig 5A-5B; Liaw 210 discloses all the limitations but silent on the source drain contact arrangement. Whereas Liaw 616 discloses a first source/drain via Fig 40B or 40C, 242, disposed on the first source/drain contact Fig 40B, 142/145, and laterally extending along the first direction to overlap the isolation wall Fig 40C, 312 ¶0027 also Fig 39-42. Liaw 210 and Liaw 616 are analogous art because they are directed to semiconductor devices having isolation structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify Liaw 210 because they are from the same field of endeavor. Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the contact/via arrangement and incorporate the teachings of Liaw 616 to improve interconnection. Regarding claim 22, Liaw 210 discloses: a second gate line Fig 5A, 110/112/114/115, extending along the second direction on the semiconductor substrate Fig 5A, and crossing the active structure Fig 5A, wherein the isolation wall is disposed between the first gate line and the second gate line Fig 5A; a second source/drain contact Fig 5A, 120/121/122/123/124/125/126/127, disposed on a second epitaxial structure Fig 5A-5B, extending along the second direction between the second gate line and the isolation wall Fig 5A-5B, and crossing the active structure Fig 5A-5B; While Liaw 616 discloses a second source/drain via, disposed on the second source/drain contact, and laterally extending along the first direction to overlap the isolation wall Fig 39-42. Regarding claim 23, Liaw 616 discloses wherein the first and second source/drain vias are spaced apart from each other along the second direction Fig 38. Regarding claim 24, Liaw 616 discloses wherein the first and second source/drain vias at most extend to a central line of the isolation wall from opposite sides of the isolation wall Fig 39, 40A-40C, 41-42. Regarding claim 25, Liaw 210 discloses: a second gate line Fig 5A, 110/112/114/115, extending along the second direction on the semiconductor substrate Fig 5A, and crossing the active structure Fig 5A, wherein the isolation wall is disposed between the first gate line and the second gate line Fig 5A; a second source/drain contact Fig 5A, 120/121/122/123/124/125/126/127, disposed on a second epitaxial structure Fig 5A-5B, extending along the second direction between the second gate line and the isolation wall Fig 5A-5B, and crossing the active structure Fig 5A-5B; While Liaw 616 discloses first source/drain via extends across the isolation wall from above and establish contact with both of the first and second source/drain contacts Fig 39-42. Regarding claim 26, Liaw 210 discloses: a second gate line Fig 5A, 110/112/114/115, extending along the second direction on the semiconductor substrate Fig 5A, and crossing the active structure Fig 5A, wherein the isolation wall is disposed between the first gate line and the second gate line Fig 5A; a second source/drain contact Fig 5A, 120/121/122/123/124/125/126/127, disposed on a second epitaxial structure Fig 5A-5B, extending along the second direction between the second gate line and the isolation wall Fig 5A-5B, and crossing the active structure Fig 5A-5B; While Liaw 616 discloses a second source/drain via, disposed on the second source/drain contact, wherein the second source/drain via is laterally spaced apart from the isolation wall Fig 38-42. Claims 7, 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US Publication No. 2016/0020210) in view of Liaw (US Publication No. 2020/0105616) and Jhan et al (US Publication No. 2023/0060454). Regarding claim 7, Liaw 210 discloses an integrated circuit, comprising: a channel structures Fig 5A, 106/108, extending along a first lateral direction on a semiconductor substrate Fig 5A; a gate line Fig 5A, 110/112/114/115, crossing the channel structures along a second lateral direction on the semiconductor substrate Fig 5A, first and second epitaxial structures ¶0026, disposed on the semiconductor substrate at opposite sides of the gate line Fig 5B, and extending through the channel structures along a vertical direction Fig 5B; first and second source/drain contacts Fig 5A, extending along the second lateral direction over the first and second epitaxial structures Fig 5A-5B, and are in contact with the first and second epitaxial structures Fig 5A-5B, respectively; an isolation wall Fig 5A, 224, cutting through the channel structures along the second lateral direction Fig 5A, wherein the first epitaxial structure and the first source/drain contact are located between the gate line and the isolation wall Fig 5A-5B. Liaw 210 discloses all the limitations but silent on the source drain contact arrangement and the channel type. Whereas Liaw 616 discloses a first source/drain via Fig 40B or 40C, 242, disposed on the first source/drain contact Fig 40B, 142/145, and laterally extending along the first direction to overlap the isolation wall Fig 40C, 312 ¶0027 also Fig 39-42. Liaw 210 and Liaw 616 are analogous art because they are directed to semiconductor devices having isolation structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify Liaw 210 because they are from the same field of endeavor. Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the contact/via arrangement and incorporate the teachings of Liaw 616 to improve interconnection. Liaw 210 and Liaw 616 disclose all the limitations but are silent on the channel type. Whereas Jhan discloses an integrated circuit, comprising: a stack of channel structures Fig 1C, 22A4-22C4, extending along a first lateral direction on a semiconductor substrate Fig 1C, 110; a gate line Fig 1C, 200, crossing the channel structures along a second lateral direction on the semiconductor substrate Fig 1C, and wrapping around each of the channel structures Fig 1C. Liaw 210, Liaw 616 and Jhan are analogous art because they are directed to semiconductor devices having isolation structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify Liaw 210 and Liaw 616 because they are from the same field of endeavor. Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the type of channel in Liaw 210 and Liaw 616, and incorporate the teachings of Jhan as an alternative channel type known in the art to improve device performance. Regarding claim 11, Liaw 210 discloses wherein a top surface of the first source/drain contact is higher than a top surface of the isolation wall Fig 5A-5B. Regarding claim 12, Jhan discloses wherein a bottom surface of the source/drain via is in contact with the source/drain contact and elevated from the top surface of the isolation wall Fig 1C-1D. Regarding claim 13, Jhan discloses wherein the source/drain via is in vertical and lateral contact with the first source/drain contact Fig 1C-1D. Allowable Subject Matter Claims 8-10, 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTINE A ENAD whose telephone number is (571)270-7891. The examiner can normally be reached Monday-Friday, 7:30 am -4:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571 272 1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
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Prosecution Timeline

Sep 03, 2023
Application Filed
Feb 18, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
94%
With Interview (+10.1%)
2y 1m
Median Time to Grant
Low
PTA Risk
Based on 1312 resolved cases by this examiner. Grant probability derived from career allow rate.

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