Prosecution Insights
Last updated: April 19, 2026
Application No. 18/460,594

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Non-Final OA §103§112
Filed
Sep 04, 2023
Examiner
SALAZ, SAMMANTHA KATELYN
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
3y 4m
To Grant
99%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allow Rate
18 granted / 19 resolved
+26.7% vs TC avg
Moderate +8% lift
Without
With
+7.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
28 currently pending
Career history
47
Total Applications
across all art units

Statute-Specific Performance

§103
44.9%
+4.9% vs TC avg
§102
31.2%
-8.8% vs TC avg
§112
14.5%
-25.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 19 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of the Claims Claims 1-20 are pending in the application and are currently being examined. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Objections Claim 2 is objected to as it states “the alloy layer is in directly contact”, which appears to be a typo meant to read “the alloy layer is in direct contact”. Appropriate action requested. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 4, 11, 14, and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 4 recites the limitation "wherein the at least one metal in the Cu alloy relative to Cu tends to be reacted with the dielectric material of the first dielectric layer" in lines 3-4. There is insufficient antecedent basis for this limitation in the claim as it is unclear how the conductive layer can react with the dielectric material when the alloy layer is between the dielectric layer and the conductive layer. For the purposes of examination, the limitation will be interpreted to read "wherein the at least one metal in the Cu alloy relative to Cu tends to be reactive with the dielectric material of the first dielectric layer". Claim 11 recites the limitation "wherein the at" in lines 3-4. There is insufficient antecedent basis for this limitation in the claim as it is unclear how the conductive layer can react with the dielectric material when the alloy layer is between the dielectric layer and the conductive layer. For the purposes of examination, the limitation will be interpreted to read "wherein the at least one metal in the Cu alloy relative to Cu tends to be reactive with the dielectric material of the first dielectric layer". Claim 14 recites the limitation "wherein the at" in lines 3-4. There is insufficient antecedent basis for this limitation in the claim as it is unclear how the conductive layer can react with the dielectric material when the alloy layer is between the dielectric layer and the conductive layer. For the purposes of examination, the limitation will be interpreted to read "wherein the at least one metal in the Cu alloy relative to Cu tends to be reactive with the dielectric material of the first dielectric layer". Claim 19 recites the limitation "wherein the at" in lines 3-4. There is insufficient antecedent basis for this limitation in the claim as it is unclear how the conductive layer can react with the dielectric material when the alloy layer is between the dielectric layer and the conductive layer. For the purposes of examination, the limitation will be interpreted to read "wherein the at least one metal in the Cu alloy relative to Cu tends to be reactive with the dielectric material of the first dielectric layer". Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-2, 5-8, 12, 15-16, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (US 2009/0017563 A1, hereafter Jiang) in view of Wang et al. (US 6,462,417 B1, hereafter Wang). Regarding claim 1, in Fig. 2G Jiang teaches a semiconductor structure, comprising: a first dielectric layer (40”, [0024]); and a conductive pattern (90” [0023] and 80” [0043]) disposed in the first dielectric layer (40”), wherein the conductive pattern comprises an alloy layer (80”) and a first conductive layer (90”), the alloy layer surrounds sidewalls and a bottom surface of the first conductive layer (90”). Jiang fails to teach a material of the alloy layer comprises an alloy of at least two metals, and at least one of the at least two metals relative to the rest of the at least two metals tends to be reacted with a dielectric material of the first dielectric layer. However, in Fig. 3 Wang teaches a semiconductor structure similar to Jiang in which an alloy layer (232, column 5 line 9) between the conductive layer (236 column 5 line 8) and the dielectric (210, column 5 line 3). The alloy layer of Wang comprises an alloy of at least two metals (copper-titanium, column 6 line 25), and at least one of the at least two metals (titanium) relative to the rest of the at least two metals (copper) tends to be reacted with a dielectric material of the first dielectric layer (Wang teaches the titanium in the barrier layer readily reacts with dielectric materials (column 5 line 31-32)). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the alloy layer of Jiang to comprise copper-titanium as taught by Wang in order to have a barrier layer that reacts with the dielectric layer to form a barrier to prevent the diffusion of copper into the dielectric material (column 5 lines 39-40). Regarding claim 2, Jiang in view of Wang teach the semiconductor structure according to claim 1. Jiang further teaches in Fig. 2G the alloy layer (80”, [0043]) is in direct contact with the first dielectric layer (40”, [0024]). Regarding claim 5, Jiang in view of Wang teach the semiconductor structure according to claim 1. Jiang further teaches an etch stop layer (30”, [0024]) disposed under the first dielectric layer (40”, [0024]) and laterally surrounding the conductive pattern (90” [0023] and 80” [0043]). Regarding claim 6, Jiang in view of Wang teach the semiconductor structure according to claim 1. Jiang further teaches a second dielectric layer (40’, [0024]) disposed under the first dielectric layer (40”, [0024]); and a second conductive layer (90’ [0023]) disposed in the second dielectric layer (40’) and electrically connecting with the conductive pattern (90” [0023] and 80” [0043]). Regarding claim 7, Jiang in view of Wang teach the semiconductor structure according to claim 6. Jiang further teaches the conductive pattern (90” [0023] and 80” [0043]) is in directly contact with the second conductive layer (90’, [0023]). Regarding claim 8, in Fig. 2G Jiang teaches a semiconductor structure, comprising: a first dielectric layer (40, [0024]) with a first conductive layer (90 [0023]) formed therein; an etch stop layer (30’, [0024]) disposed over the first dielectric layer and the first conductive layer, a second dielectric layer (40’, [0024]) disposed over the etch stop layer (30’); and a via pattern (90’ [0023] and 80’ [0043]) penetrating the second dielectric layer (40’) and the etch stop layer (30’) and electrically connecting with the first conductive layer (40’), wherein the via pattern comprises a second conductive layer (90’ [0023]) and a first alloy layer (80’ [0043]) surrounding sidewalls and a bottom surface of the second conductive layer (90’). Jiang fails to teach a material of the alloy layer comprises an alloy of at least two metals, and at least one of the at least two metals relative to the rest of the at least two metals tends to be reacted with a dielectric material of the first dielectric layer. However, in Fig. 3 Wang teaches a semiconductor structure similar to Jiang in which an alloy layer (232, column 5 line 9) between the conductive layer (236 column 5 line 8) and the dielectric (210, column 5 line 3). The alloy layer of Wang comprises an alloy of at least two metals (copper-titanium, column 6 line 25), and at least one of the at least two metals (titanium) relative to the rest of the at least two metals (copper) tends to be reacted with a dielectric material of the first dielectric layer (Wang teaches the titanium in the barrier layer readily reacts with dielectric materials including silicon nitrides (column 5 line 31-32 and line 36). Silicon nitride is what the etch stop layer of Jiang can be made from [0024]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the alloy layer of Jiang to comprise copper-titanium as taught by Wang in order to have a barrier layer that reacts with the dielectric layer and the etch stop layer to form a barrier to prevent the diffusion of copper into the dielectric material (column 5 lines 39-40). Regarding claim 12, Jiang in view of Wang teach the semiconductor structure of claim 8. Jiang further teaches a third dielectric layer (40”, [0024]) disposed over the second dielectric layer (40’, [0024]) and the via pattern (90’ [0023] and 80’ [0043]); and a wiring pattern penetrating (90” [0023] and 80” [0043]) the third dielectric layer and electrically connecting with the via pattern (90’ and 80’), wherein the wiring pattern (90” and 80”) comprises a third conductive layer (90”) and a second alloy layer (80”) surrounding sidewalls and a bottom surface of the third conductive layer (90”). As the wiring pattern does not appear structurally different from the via pattern, the structures described by Jiang read on the claim under BRI. Jiang fails to teach a material of the second alloy layer comprises an alloy of at least two metals, and at least one of the at least two metals relative to the rest of the at least two metals tends to be reacted with a dielectric material of the first dielectric layer. However, in Fig. 3 Wang teaches a semiconductor structure similar to Jiang in which an alloy layer (232, column 5 line 9) between the conductive layer (236 column 5 line 8) and the dielectric (210, column 5 line 3). The alloy layer of Wang comprises an alloy of at least two metals (copper-titanium, column 6 line 25), and at least one of the at least two metals (titanium) relative to the rest of the at least two metals (copper) tends to be reacted with a dielectric material of the first dielectric layer (Wang teaches the titanium in the barrier layer readily reacts with dielectric materials including silicon nitrides (column 5 line 31-32 and line 36). Silicon nitride is what the etch stop layer of Jiang can be made from [0024]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the second alloy layer of Jiang to comprise copper-titanium as taught by Wang in order to have a barrier layer that reacts with the dielectric layer and the etch stop layer to form a barrier to prevent the diffusion of copper into the dielectric material (column 5 lines 39-40). Regarding claim 15, Jiang teaches a method of manufacturing a semiconductor structure, comprising: forming an opening (process shown in Fig. 23) extending through a first dielectric layer (40, [0024]); and performing a single damascene process (while Jiang teaches a dual damascene process, they teach that a single damascene process is also viable [0023]) to form a conductive pattern (90 [0023] and 80 [0043]) in the opening, wherein the conductive pattern comprises an alloy layer (80) and a first conductive layer (90), the alloy layer (80) surrounds sidewalls and a bottom surface of the first conductive layer (90). Jiang fails to teach a material of the alloy layer comprises an alloy of at least two metals, and at least one of the at least two metals relative to the rest of the at least two metals tends to be reacted with a dielectric material of the first dielectric layer. However, in Fig. 3 Wang teaches a semiconductor structure similar to Jiang in which an alloy layer (232, column 5 line 9) between the conductive layer (236 column 5 line 8) and the dielectric (210, column 5 line 3). The alloy layer of Wang comprises an alloy of at least two metals (copper-titanium, column 6 line 25), and at least one of the at least two metals (titanium) relative to the rest of the at least two metals (copper) tends to be reacted with a dielectric material of the first dielectric layer (Wang teaches the titanium in the barrier layer readily reacts with dielectric materials (column 5 line 31-32)). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the alloy layer of Jiang to comprise copper-titanium as taught by Wang in order to have a barrier layer that reacts with the dielectric layer to form a barrier to prevent the diffusion of copper into the dielectric material (column 5 lines 39-40). Regarding claim 16, Jiang in view of Wang teach the method of claim 15. Jiang further teaches wherein the step of performing the single damascene process comprises: forming the alloy layer (80, [0043]) lining sidewalls and a bottom surface of the opening (in Fig. 2E and 2F) and locating over the first dielectric layer (40, [0024]); filling up the opening with the first conductive layer (90, [0023]); and performing a planarization process (chemical mechanical polishing [0043]) to remove portions of the first conductive layer (90) and the alloy layer over (80) the first dielectric layer (40). Regarding claim 20, Jiang in view of Wang teach the method of claim 15. Wang further teaches a thickness of the alloy layer (80 of Jiang, [0043]) ranges from about 5 Å to about 50 Å (column 5 line 58). Specifically, Wang teaches less than 100 angstroms, which fully captures the necessary range. Claim(s) 3, 9, 10, 13, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jiang in view of Wang, and further in view of Yang et al. (US 2021/0375749 A1, hereafter Yang, and in view of Nowak (US 5,250,834 A). Regarding claim 3, Jiang in view of Wang teach the semiconductor structure of claim 1. Jiang in view of Wang fail to disclose the at least two metals are selected from Co, Ru, Ta, Ti, W, Mo, Zn, Al, Mn, Zr, Hf, Nb, V, Cr, Sc, Y and Si. However, Yang discloses in Fig. 3 that another suitable alloy layer (barrier layer 212, [0021]) in interconnect structures is cobalt tantalum [0021]. Both cobalt and tantalum react with certain dielectric materials, as Nowak teaches in (column 4 lines 54-56). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the alloy layer of Jiang in view of Wang to be made from cobalt tantalum as taught by Yang to still get the reacted layer as in claim 1. Regarding claim 9, Jiang in view of Wang teach the semiconductor structure of claim 8. Jiang in view of Wang fail to disclose the at least two metals are selected from Co, Ru, Ta, Ti, W, Mo, Zn, Al, Mn, Zr, Hf, Nb, V, Cr, Sc, Y and Si. However, Yang discloses in Fig. 3 that another suitable alloy layer (barrier layer 212, [0021]) in interconnect structures is cobalt tantalum [0021]. Both cobalt and tantalum react with certain dielectric materials, as Nowak teaches in (column 4 lines 54-56). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the alloy layer of Jiang in view of Wang to be made from cobalt tantalum as taught by Yang to still get the reacted layer as in claim 8. Regarding claim 10, Jiang in view of Wang and in further view of Nowak teach the semiconductor structure of claim 8, wherein the material of the alloy layer (barrier layer 212 of Nowak, [0021]) includes Co-Ta alloy [0021]. Regarding claim 13, Jiang in view of Wang teach the semiconductor structure of claim 12. Jiang in view of Wang fail to disclose the at least two metals of the second alloy are selected from Co, Ru, Ta, Ti, W, Mo, Zn, Al, Mn, Zr, Hf, Nb, V, Cr, Sc, Y and Si. However, Yang discloses in Fig. 3 that another suitable alloy layer (barrier layer 212, [0021]) in interconnect structures is cobalt tantalum [0021]. Both cobalt and tantalum react with certain dielectric materials, as Nowak teaches in (column 4 lines 54-56). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the second alloy layer of Jiang in view of Wang to be made from cobalt tantalum as taught by Yang to still get the reacted layer as in claim 12. Regarding claim 18, Jiang in view of Wang teach the method of claim 15. Jiang in view of Wang fail to disclose the at least two metals are selected from Co, Ru, Ta, Ti, W, Mo, Zn, Al, Mn, Zr, Hf, Nb, V, Cr, Sc, Y and Si. However, Yang discloses in Fig. 3 that another suitable alloy layer (barrier layer 212, [0021]) in interconnect structures is cobalt tantalum [0021]. Both cobalt and tantalum react with certain dielectric materials, as Nowak teaches in (column 4 lines 54-56). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the alloy layer of Jiang in view of Wang to be made from cobalt tantalum as taught by Yang to still get the reacted layer as in claim 15. Claim(s) 4, 14, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jiang in view of Wang, and further in view of Xu et al. (US 2016/0211216 A1, hereafter Xu). Regarding claim 4, Jiang in view of Wang teach the semiconductor structure according to claim 1. Wang further teaches in Fig. 3, a material of the first conductive layer (90”, [0023]) includes Cu alloy including at least one metal selected from Mn, Nb, Zr, Al, Ti, Ru, Mo, W, Cr and Zn (the metal conductor 90” can comprise Cu/Al alloys, [0043]). While Jiang is silent on the at least one metal in the Cu alloy relative to Cu (Al) tends to be reactive with the dielectric material of the first dielectric layer, Aluminum is known to be reactive with dielectric materials, as Xu states in [0047]. Regarding claim 14, Jiang in view of Wang teach the semiconductor structure according to claim 12. Wang further teaches in Fig. 3, a material of the third conductive layer (90”, [0023]) includes Cu alloy including at least one metal selected from Mn, Nb, Zr, Al, Ti, Ru, Mo, W, Cr and Zn (the metal conductor 90” can comprise Cu/Al alloys, [0043]). While Jiang is silent on the at least one metal in the Cu alloy relative to Cu (Al) tends to be reactive with the dielectric material of the first dielectric layer, Aluminum is known to be reactive with dielectric materials, as Xu states in [0047]. Regarding claim 19, Jiang in view of Wang teach the method of claim 15. Wang further teaches in Fig. 3, a material of the first conductive layer (90, [0023]) includes Cu alloy including at least one metal selected from Mn, Nb, Zr, Al, Ti, Ru, Mo, W, Cr and Zn (the metal conductor 90 can comprise Cu/Al alloys, [0043]). While Jiang is silent on the at least one metal in the Cu alloy relative to Cu (Al) tends to be reactive with the dielectric material of the first dielectric layer, Aluminum is known to be reactive with dielectric materials, as Xu states in [0047]. Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jiang in view of Wang, and further in view of Noguchi et al. (US 2020/0279957 A1). Regarding claim 11, Jiang in view of Wang teach the semiconductor structure according to claim 8. Wang further teaches in Fig. 3, a material of the first conductive layer (90’, [0023]) includes Cu alloy including at least one metal selected from Mn, Nb, Zr, Al, Ti, Ru, Mo, W, Cr and Zn (the metal conductor 90” can comprise Cu/Al alloys, [0043]). While Jiang is silent on the at least one metal in the Cu alloy relative to Cu (Al) tends to be reactive with the dielectric material of the first dielectric layer, Aluminum is known to be reactive with dielectric materials, as Xu states in [0047]. Jiang is also silent on the at least one metal in the Cu alloy relative to Cu (Al) tends to be reactive with the etch stop layer, and Noguchi teaches the aluminum would diffuse into the silicon nitride to provide electron trap sites. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first conductive layer to be CuAl as Jiang teaches. Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jiang in view of Wang as applied to claim 16 above, and further in view of Hussey et al. (US 2022/0347968 A1, hereafter Hussey). Regarding claim 17, Jiang in view of Wang teach the method of claim 16. Jiang further teaches the step of forming the alloy layer (80, [0043]) comprises: performing a deposition process to form the alloy layer (as seen in Fig. 2F, [0043]). Jiang in view of Wang fail to teach performing a treatment process on the alloy layer, wherein the treatment process is a plasma process or a soaking process. However, Hussey teaches a method of applying a coating (similar to the alloy layer) in which a plasma treatment is performed after deposition in order to set the coating. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Wang in view of Jiang to include the plasma treatment of Hussey to set the alloy layer onto the dielectric layer. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SAMMANTHA K SALAZ/Examiner, Art Unit 2892 /NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
Read full office action

Prosecution Timeline

Sep 04, 2023
Application Filed
Mar 12, 2026
Non-Final Rejection — §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
99%
With Interview (+7.7%)
3y 4m
Median Time to Grant
Low
PTA Risk
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