DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species 1 in the reply filed on 1/9/26 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Yu et al (US 2021/0407942).
1. (Original) A semiconductor device, comprising:
a first die (Fig. 5-15 (70) and [0034]), having a first side (top) comprising a plurality of first connecting structures (Fig.5-15 (96) and [0040]) and a second side (bottom) comprising a plurality of second connecting structures (Fig.12-15 (136) and [0052]), the first side (top of 70) being opposite to the second side (bottom of 70) (See Fig.12);
a second die (Fig.2/6/12-15 (50) and [0016/0034]), having a third side (top) comprising a plurality of third connecting structures (Fig.2/6/12-15 (66) and [0033]), the plurality of third connecting structures (Fig.6/12-15 (66) and [0033]) being in contact with the plurality of first connecting structures (Fig.6/12-15 (96) and [0040]) of the first die (Fig. 6/12-15 (70) and [0034]); and
a third die (Fig.13-15 (150) and [0053]), having a fourth side (top) comprising a plurality of fourth connecting structures (Fig.14 (186) and [0055]), the plurality of fourth connecting structures (Fig.15 (186) and [0055]) being in contact with the plurality of second connecting structures (Fig.15 (136) and [0052]) of the first die (Fig.15 (70) and [0034]),
wherein a first pitch (Fig.19A-19B (P1) and [0061]) of the plurality of first connecting structures (Fig 19A (96) and [0040]) and a second pitch (Fig.19A-19B (P1- the pitch for 66 and 96 are the same) and [0061]) of the plurality of third connecting structures (Fig.19A (66) and [0033]) are less than a third pitch (Fig.19A-19B (P2) and [0061]) of the plurality of fourth connecting structures (Fig.19A (186) and [0055]).
2. (Original) The semiconductor device of claim 1, wherein a first bonding interface between the plurality of first connecting structures (Fig.6/12-15 (96) and [0040]) and the plurality of third connecting structures (Fig.2/6/12-15 (66) and [0033]) comprising a first metal-to-metal bonding interface and a first dielectric-to-dielectric bonding interface [0041- teaching metal to metal and dielectric to dielectric bonding], and a second bonding interface between the plurality of second connecting structures (Fig.15 (136) and [0052]) and the plurality of fourth connecting structures (Fig.15 (186) and [0055]) comprising a second metal-to-metal bonding interface and a second dielectric-to-dielectric bonding interface [0056- teaching metal to metal and dielectric to dielectric bonding].
3. (Original) The semiconductor device of claim 1, further comprising: an insulating encapsulation (Fig.40 (522) and [0087]), laterally covering the first die (Fig. 5-15 (70) and [0034]) and the second die (Fig.2/6/12-15 (50) and [0016/0034]), wherein a sidewall of the insulating encapsulation (Fig.40 (522) and [0087]) is substantially aligned to a sidewall of the third die (Fig.13-15 (150) and [0053]).
4. (Original) The semiconductor device of claim 1, further comprising: an insulating encapsulation (Fig.40 (522/402) and [0087/0075]), laterally covering the third die (Fig.13-15 (150) and [0053]), wherein a sidewall of the insulating encapsulation (Fig.40 (402) and [0075]) is substantially aligned to a sidewall of the first die (Fig. 5-15 (70) and [0034]) and a sidewall of the second die (Fig.2/6/12-15 (50) and [0016/0034]).
5. (Original) The semiconductor device of claim 1, further comprising: a first insulating encapsulation (Fig.40 (522/402) and [0087/0075]), laterally covering the first die (Fig. 5-15 (70) and [0034]) and the second die (Fig.2/6/12-15 (50) and [0016/0034]); and a second insulating encapsulation (Fig.40 (522/402) and [0087/0075]), laterally covering the third die (Fig.13-15 (150) and [0053]), wherein a sidewall of the first insulating encapsulation is substantially aligned to a sidewall of the second insulating encapsulation (Fig.40 (522/402) and [0087/0075]).
6. (Original) The semiconductor device of claim 1, wherein a sidewall of the first die (Fig. 5-15 (70) and [0034]), a sidewall of a second die (Fig.2/6/12-15 (50) and [0016/0034]) and a sidewall of third die (Fig.13-15 (150) and [0053]) are substantially aligned with each other (Fig.15).
7. (Original) The semiconductor device of claim 1, further comprising: a plurality of conductive terminals (Fig.17-18 (191) and [0059]), disposed on and electrically coupled to a plurality of fifth connecting structures (Fig.17-18 (193) and [0059]) distributed on a fifth side (bottom see Fig.13-14- but flipped in Fig.s 17-18) of the third die (Fig.13-15 (150) and [0053]), the fourth side (top in Fig.s 13-14/ bottom in Fig.17-18) being opposite to the fifth side (bottom in Fig.13/14/ top in Fig.17-18).
8. (Original) The semiconductor device of claim 7, wherein a material of the plurality of fifth connecting structures (Fig.17-18 (193) and [0059]) comprises aluminum [0058].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yu et al (US 11581281); Zhou et al (US 10665581); Chen et al (US 20200328200; US 10727217; US 11088131) teach similar structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LAURA M MENZ/Primary Examiner, Art Unit 2813
3/15/26
Prosecution Insights