DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. Applicant’s amendment to the claims, filed on August 22, 2021, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
3. Applicant’s arguments/remarks, see pgs. 2-6, with respect to the immediate allowance of the current application have been fully considered but are not persuasive.
Pertaining to the Applicant’s arguments/remarks, pgs. 2-6, regarding the claimed limitations “the active regions are arranged in pairs along the second direction … a featured portion of each active region right below an intersecting one of the word lines has a first side closely adjacent to the other active region in the same pair by the first spacing as well as a second side separated from an adjacent pair of the active regions by the second spacing, and has a inclined top surface ascending from the second side to the first side”.
Applicant argues that the interpretation of the prior art for the pairs of active regions is improper and exceeds the scope of BRI:
The Examiner disagrees as indicated in the office action, the claimed “regions” are not defined with sufficient specificity as argued by pointing to the drawings of the Applicant’s specification such as to distinguish from the outstanding rejection. The Applicant’s drawing of Fig. 1C shows that the pair of active regions are entirely separated by at least the isolation structure element 102 which is not claimed; although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The limitation “region” is not provided with a special definition in the written description such as to limit the meaning of the word beyond what is presented in the claims. Moreover, S1 explicitly shows an interpretation of active regions elements M1 see [0034] “region M1” which is within element 103a. A region without limitations on specific structural boundaries is by definition an area which is determined by whomever is drawing the region. The limitation “active” which precedes the limitation “regions” is met by pertaining to an active area of the substrate which is also disclosed by the prior art.
The argument stating the prior art does not disclose a “physical spacing between two distinct active regions defined by an isolation structure” would be found persuasive if claimed, for example, by stating “each active region of the pair of active regions are entirely separated from each other by an isolation structure”. However, the manner in which the claims are currently recited does not recite such limitations with sufficient specificity such as to distinguish from the prior art.
Note by the Examiner
4. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim 1-4, 7, and 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 2022/0262803 A1), hereinafter as J1, in view of Seo et al. (US 2008/0079070 A1), hereinafter as S1
6. Regarding Claim 1, J1 discloses a memory device (see in particular Figs. 1-3 and [0011] “memory device”), comprising:
active regions (element ACT regions between elements 105, see [0026] “active regions ACT may be defined by an element separation film 105 formed inside the substrate 100”), defined in a semiconductor substrate (element 100, see [0026]) by an isolation structure (element 105, see [0026]), and are arranged as an array (see Fig. 1) along a first direction (first D2 direction) and a second direction (second D1 direction), wherein each of the active regions extends along a third direction (third D3 direction) intersected with the first direction and the second direction (see Fig. 1); and
word lines (elements WL,112, see [0028] “word line WL” and see [0040] “the gate electrode 112 may correspond to the word line WL”), formed in the semiconductor substrate (see Fig. 3), and extending through the active regions along the second direction (see Figs. 1, 3),
wherein the active regions are arranged along the second direction (see Fig. 1).
J1 does not explicitly disclose wherein the active regions are arranged in pairs, the active regions in the same pair are closely adjacent to each other by a first spacing, adjacent pairs of the active regions are separated from each other by a second spacing greater than the first spacing, a featured portion of each active region right below an intersecting one of the word lines has a first side closely adjacent to the other active region in the same pair by the first spacing as well as a second side separated from an adjacent pair of the active regions by the second spacing, and has a inclined top surface ascending from the second side to the first side.
S1 discloses (see Figs. 1-11 in particular see Fig. 10 and [0040] “The data storage element 136 may be a data storage unit of a volatile memory device”) wherein the active regions are arranged in pairs (two regions in the active region area of element 203a selected as a left half and right half with a small space between, see [0042] “active region 203a” – note, the manner in which the claim is currently recited does not provide specific boundaries which define the pairs of active regions such as to distinguish from the prior art of record), the active regions in the same pair are closely adjacent to each other by a first spacing (small space between the left half and right half arbitrarily determined as the two regions do not have claimed boundaries), adjacent pairs of the active regions are separated from each other by a second spacing greater than the first spacing (separated by an entire width of elements 209 see Fig. 1, 10), a featured portion (portion of the active layer vertically overlapping the word line) of each active region right below an intersecting one of the word lines (element 224 intersecting the active region element 203a) has a first side (selected as a right side) closely adjacent to the other active region (selected as the right element N1) in the same pair by the first spacing as well as a second side (selected as a left side) separated from an adjacent pair of the active regions by the second spacing, and has a inclined top surface ascending from the second side to the first side (see Fig. 10 the left second side has a top surface which is slanted upwards such that it is ascending in height from the second left side to the first right side).
The shape of the upper surface of the active layer as taught by S1 is incorporated as a shape of the upper surface of the active layer of J1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S1 with J1 because the combination provides a greater effective channel width and can improve on-current characteristics, body effect, and sub-threshold swing characteristics of a transistor as well as a short channel effect (see S1 [0051]); furthermore, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known upper surface of an active layer in a similar memory device for another to obtain predictable results (see S1 Fig. 10 and [0051]).
7. Regarding Claim 2, J1, S1 disclose the memory device according to claim 1, wherein the featured portion of each active region protrudes with respect to portions of the isolation structure lying right below the word lines (see S1 Fig. 10 portions of element 203a protrude to a taller height than isolation structure element 209, see [0068] “trench isolation layer 209”).
8. Regarding Claim 3, J1, S1 disclose the memory device according to claim 1, wherein first sections (see S1 Fig. 10 selected as C1 sections) of the word lines extending through the active regions are formed to a depth less than a depth to which second sections (see S1 Fig. 10 selected as C2 sections) of the word lines extending through the isolation structure are formed (see Fig. 10 the C1 section portion of element 224 is formed to a depth less than a depth in the C2 section portion).
9. Regarding Claim 4, J1, S1 disclose the memory device according to claim 3, wherein the first sections of the word lines respectively have an inclined bottom surface tilting along the second direction (see S1 Fig. 10).
10. Regarding Claim 7, J1, S1 disclose the memory device according to claim 1, wherein the featured portions of the active region in the same pair are symmetric with respect to a central axis in between (see J1 Fig. 10 symmetric with respect to a center of 203a).
11. Regarding Claim 8, J1, S1 disclose the memory device according to claim 1, wherein the featured portions of adjacent ones of the active regions separated from each other by the second spacing are symmetric with respect to a central axis in between (see J1 Fig. 10 symmetric with respect to a center of 203a and see S1 Fig. 1 the array is formed with repeated structures such that the spacings are also symmetric).
12. Regarding Claim 9, J1, S1 disclose the memory device according to claim 1, further comprising: insulating structures (see J1 Fig. 3 elements 105 and S1 Fig. 10 elements 209), disposed in the isolation structure and separated from one another, wherein each active region extends between two of the insulating structures along the third direction, and the word lines extend through the insulating structures (see J1 Figs. 1,3 and S1 Fig. 10).
13. Regarding Claim 10, J1, S1 disclose the memory device according to claim 9, wherein each insulating structure is placed in between two of the active regions separated from each other by the second spacing (see J1 Figs. 1,3 and S1 Fig. 10).
14. Regarding Claim 11, J1, S1 disclose the memory device according to claim 1, further comprising (see J1 Fig. 1):
bit lines (elements BL, see [0024] “bit line BL”), extending along the first direction over the semiconductor substrate (see Fig. 1), and overlapping the active regions (see Fig. 1 overlapping element ACT).
15. Regarding Claim 12, J1, S1 disclose the memory device according to claim 1, wherein each active region is separated from an intersecting one of the word lines by a gate dielectric layer (see J1 Fig. 1 element 111, see [0041] “gate insulating film 111”).
16. Regarding Claim 13, J1, S1 disclose the memory device according to claim 1, further comprising:
insulating plugs (see J1 Fig. 3 element 114 and see [0044] “The gate capping pattern 114 may fill the gate trench 110t that remains after the gate electrode 112 and the gate capping conductive film 113 are formed”), disposed on the word lines, and respectively extending along one of the word lines (see [0044]).
17. Claims 1 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 2022/0262803 A1), hereinafter as J1, in view of Seo et al. (US 2008/0079070 A1), hereinafter as S1
18. Regarding Claim 1, J1 discloses a memory device (see in particular Figs. 1-3 and [0011] “memory device”), comprising:
active regions (element ACT regions between elements 105, see [0026] “active regions ACT may be defined by an element separation film 105 formed inside the substrate 100”), defined in a semiconductor substrate (element 100, see [0026]) by an isolation structure (element 105, see [0026]), and are arranged as an array (see Fig. 1) along a first direction (first D2 direction) and a second direction (second D1 direction), wherein each of the active regions extends along a third direction (third D3 direction) intersected with the first direction and the second direction (see Fig. 1); and
word lines (elements WL,112, see [0028] “word line WL” and see [0040] “the gate electrode 112 may correspond to the word line WL”), formed in the semiconductor substrate (see Fig. 3), and extending through the active regions along the second direction (see Figs. 1, 3),
wherein the active regions are arranged along the second direction (see Fig. 1).
J1 does not explicitly disclose wherein the active regions are arranged in pairs, the active regions in the same pair are closely adjacent to each other by a first spacing, adjacent pairs of the active regions are separated from each other by a second spacing greater than the first spacing, a featured portion of each active region right below an intersecting one of the word lines has a first side closely adjacent to the other active region in the same pair by the first spacing as well as a second side separated from an adjacent pair of the active regions by the second spacing, and has a inclined top surface ascending from the second side to the first side.
S1 discloses (see Figs. 1-11 in particular see Fig. 10 and [0040] “The data storage element 136 may be a data storage unit of a volatile memory device”) wherein the active regions are arranged in pairs (two regions in the active region area of element 203a selected as a left half and right half with a small space between, see [0042] “active region 203a” – note, the manner in which the claim is currently recited does not provide specific boundaries which define the pairs of active regions such as to distinguish from the prior art of record), the active regions in the same pair are closely adjacent to each other by a first spacing (small space between the left half and right half arbitrarily determined as the two regions do not have claimed boundaries), adjacent pairs of the active regions are separated from each other by a second spacing greater than the first spacing (separated by an entire width of elements 209 see Fig. 1, 10), a featured portion (left element C2, C3 portion) of each active region right below an intersecting one of the word lines (element 224 intersecting the active region element 203a) has a first side (selected as a right side) closely adjacent to the other active region (selected as the right element N1) in the same pair by the first spacing as well as a second side (selected as a left side) separated from an adjacent pair of the active regions by the second spacing, and has a inclined top surface ascending from the second side to the first side (see Fig. 10 the left second side has a top surface which is slanted upwards such that it is ascending in height from the second left side to the first right side).
The shape of the upper surface of the active layer as taught by S1 is incorporated as a shape of the upper surface of the active layer of J1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S1 with J1 because the combination provides a greater effective channel width and can improve on-current characteristics, body effect, and sub-threshold swing characteristics of a transistor as well as a short channel effect (see S1 [0051]); furthermore, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known upper surface of an active layer in a similar memory device for another to obtain predictable results (see S1 Fig. 10 and [0051]).
19. Regarding Claim 5, J1, S1 disclose the memory device according to claim 1, wherein (see S1 Fig. 10) the word lines extend to the first side of the featured portion of each active region by a first depth (first ride side portion of element C3), and extend to the second side of the featured portion of each active region by a second depth greater than the first depth (second left side portion of element C2) (element C2 left side portion has a greater depth than right side element C3 portion depth for element 224).
20. Regarding Claim 6, J1, S1 disclose the memory device according to claim 1, wherein the featured portion of each active region is an asymmetric structure (see S1 Fig. 10 left element C2 and C3 portions are asymmetric).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SAMUEL PARK/Examiner, Art Unit 2818
Prosecution Insights