Prosecution Insights
Last updated: October 26, 2026
Application No. 18/460,621

SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME

Final Rejection §103
Filed
Sep 04, 2023
Priority
Sep 19, 2022 — CN 202211138172.6
Examiner
FAN, SU JYA
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Stats Chippac Pte. Ltd.
OA Round
2 (Final)
76%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
725 granted / 956 resolved
+7.8% vs TC avg
Moderate +11% lift
Without
With
+11.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
46 currently pending
Career history
1020
Total Applications
across all art units

Statute-Specific Performance

§101
4.3%
-35.7% vs TC avg
§103
50.3%
+10.3% vs TC avg
§102
22.9%
-17.1% vs TC avg
§112
19.8%
-20.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 956 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Response to Amendment The following office action is in response to the amendment and remarks filed on 8/6/26. Applicant’s amendment to claims 1, 3 and 14 is acknowledged. Applicant’s cancellation of claims 6-13 is acknowledged. Claims 1-5 and 14-16 are pending and subject to examination at this time. Response to Arguments Applicant's arguments filed 8/6/26 have been fully considered but they are not persuasive. In response to Applicant’s arguments on “cutting, by the wiring cutting component”: It would have been obvious to one of ordinary skill in the art that in Zakel[2]’s fig. 2 the Singulation Unit implicitly performs a cutting process on a solder wire because (i) To singulate means to cut; and (ii) Korean publication KR 19980053197 A is evidence that wire cutting a solder wire is an art recognized process to form a conductive bump. In response to Applicant’s arguments that Zakel[2] melts the solder ball during the jetting process: The secondary reference, Zakel[2] is used to teach a solder supplying component. The Zakel[2] is not used to teach the limitation “melting, by the light source, the portion of the solder wire to form the second conductive bump”. The primary reference, Zakel[1] is used to teach the limitation “melting, by the light source, the portion of the solder wire to form the second conductive bump”, as set forth below in claim 1. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3, 5 and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., US Publication No. 2018/0323170 A1 (of record) in view of Zakel[1] et al., US Publication No. 2003/0235976 A1 (of record), Zakel[2] et al., "High Speed Laser Solder Jetting Technology for Optoelectronics and MEMS Packaging" (2002): pages 1-7 (of record) and in further view of KR 19980053197 A (see attached English machine translation). Kim teaches: 1. A method for making a semiconductor device, comprising (see fig. 11): providing a package comprising: a substrate (910) comprising a first substrate surface and a second substrate surface opposite to the first substrate surface; a first conductive bump (981) formed on the first substrate surface; and a first encapsulant (950) disposed on the first substrate surface and encapsulating the first conductive bump (981); forming a groove (955) in the first encapsulant (950) to expose at least a portion of the first conductive bump (981); and forming a second conductive bump (982) on the exposed portion of the first conductive bump (981)… See Kim at para. [0001] – [0200], figs. 1-22. Regarding claim 1: Kim does not expressly teach: The second conductive bump is formed :using a laser soldering apparatus”, and wherein the laser soldering apparatus comprises a light source configured for irradiating a laser beam, a solder supplying component configured for supplying a solder wire, and a wire cutting component, and forming the second conductive bump on the exposed portion of the first conductive bump comprises: cutting, by the wire cutting component, a portion of the solder wire supplied by the solder supplying component; supplying, by the solder supplying component, the portion of the solder wire onto the exposed portion of the first conductive bump; and melting, by the light source, the portion of the solder wire to form the second conductive bump. In an analogous art, Zakel[1] teaches: (see figs. 1-6) a first conductive bump (31) formed on a first substrate surface (20); and a first encapsulant (32) disposed on the first substrate surface and encapsulating the first conductive bump; forming a groove (34) in the first encapsulant to expose at least a portion of the first conductive bump; and forming a second conductive bump (35) on the exposed portion of the first conductive bump using a laser soldering apparatus (30 in fig. 5), wherein the laser soldering apparatus comprises a light source configured for irradiating a laser beam (e.g. para. [0037]), and forming the second conductive bump on the exposed portion of the first conductive bump comprises: (see fig. 5) supplying…the portion of the solder (35) onto the exposed portion of the first conductive bump (31); and (see fig. 6) melting, by the light source (30), the portion of the solder wire to form the second conductive bump (e.g. para. [0039] – [0041]) See Zakel[1] at para. [0035] – [0041], In an analogous art, Zakel[2] teaches: (see fig. 2) a light source (e.g. Nd:YAG laser) configured for irradiating a laser beam; a solder supplying component (e.g. Singulation Unit) configured for supplying a solder wire, and a wire cutting component (e.g. Implicit in Singulation Unit because to singulate means to cut.), cutting, by the wire cutting component (e.g. Implicit in Singulation Unit because to singulate means to cut.), a portion of the solder wire supplied by the solder supplying component (e.g. See page 3: “…the Laser Jet is using preformed solder balls which are singulated and jetted via a capillary onto the substrate.); supplying, by the solder supplying component (e.g. Singulation Unit), the portion of the solder wire… See Zakel[2] at page 3. In an analogous art, KR 19980053197 A teaches (see fig. 1) wire cutting a solder wire (4) to form a conductive bump (8). See English machine translation at page 1, section Solution and also pages 3-5. Cutting a solder wire to form a conductive bump can “improve productivity” See page 2, section Technical Field. Also see page 5, section Advantageous Effects. It would have been obvious to one of ordinary skill in the art that in Zakel[2] the Singulation Unit implicitly performs a cutting process on a solder wire because (i) To singulate means to cut; and (ii) KR 19980053197 A is evidence that wire cutting a solder wire is an art recognized process to form a conductive bump. Regarding claim 2: Kim further teaches: 2. The method of claim 1, wherein the second conductive bump (982) protrudes outside the groove (955), fig. 11C. Zakel[1] also teaches: 2. The method of claim 1, wherein the second conductive bump (35) protrudes outside the groove (34), fig. 5. Kim further teaches: 3. The method of claim 1, wherein the package further comprises: a first electronic component (970) mounted on the first substrate surface and encapsulated by the first encapsulant (950); a second electronic component (920) mounted on the second substrate surface; and a second encapsulant (940) disposed on the second substrate surface and encapsulating the second electronic component (920), fig. 11C. Kim further teaches: 5. The method of claim 1, wherein forming the groove in the first encapsulant comprises: forming the groove in the first encapsulant using a laser ablation process, para. [0109]. Regarding claim 14: Zakel[1] further teaches: 14. The method of claim 1, further comprising: pre-heating, by the light source (e.g. Nd:YAG laser), the first conductive bump (29 in fig. 1 becomes 31 in fig. 2) to a predetermined temperature, para. [0037]. Regarding claim 15: Zakel[1] further teaches: 15. The method of claim 1, further comprising: post-heating, by the light source (30), the first conductive bump (31) and the second conductive bump (35) to integrate them together, para. [0039], fig. 6. Kim further teaches: 16. A semiconductor device, wherein the semiconductor device is made using the method of claim 1, fig. 11E. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Kim with the teachings of Zakel[1] because “Compared with the known method, the method according to the invention thus has the advantage that as a result of the melting of the joining material moldings using laser energy, locally delimited, exactly definable thermal energy can be produced in the joining material moldings…” See Zakel[1] at para. [0011]. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Kim with the teachings of Zakel[2] because “This technology fulfills all the needs of fluxless soldering, local heating and reflow, no mechanical contact and stress during soldering, high solder alloy flexibility and capability of 3D-packaging.” See Zakel[2] at Abstract. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Kim with the teachings of KR 19980053197 A because cutting a solder wire to form a conductive bump can “improve productivity” See page 2, section Technical Field. Also see page 5, section Advantageous Effects. Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Zakel[1], Zakel[2] and KR 19980053197 A, as applied to claim 1 above, in further view of Healy et al., US Publication No. 014/0196940 A1 (of record). Regarding claim 4: Kim, Zakel[1], Zakel[2] and KR 19980053197 A teach all the limitations of claim 1 above, and Kim further teaches the groove (955) exposes a top surface of the first conductive bump (981). Kim does not expressly teach the groove exposes a portion of a lateral surface of the first conductive bump. In an analogous art, Healy teaches: (see fig. 5) a groove (305+308b) exposes a top surface and a portion of a lateral surface of a first conductive bump (306b). See Healy at para. [0058] – [0070], also see fig. 6. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Kim with the teachings of Healy because “…allowing a path to relieve pressure created when moisture gets entrapped in through mold vias, during the manufacturing process, while also reducing the risk of solder shorts between adjacent solder balls located in the through mold vias…As a result, process margins and risks associated with surface mount technology (SMT) may be improved and provide more flexibility on inventory staging.” See Healy at Abstract. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini, can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Michele Fan/ Primary Examiner, Art Unit 2818 29 September 2026
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Prosecution Timeline

Sep 04, 2023
Application Filed
May 07, 2026
Non-Final Rejection mailed — §103
Aug 06, 2026
Response Filed
Oct 13, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
76%
Grant Probability
87%
With Interview (+11.1%)
2y 7m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 956 resolved cases by this examiner. Grant probability derived from career allowance rate.

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