Prosecution Insights
Last updated: July 17, 2026
Application No. 18/460,621

SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME

Non-Final OA §103
Filed
Sep 04, 2023
Priority
Sep 19, 2022 — CN 202211138172.6
Examiner
FAN, SU JYA
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
STATS ChipPAC Pte. Ltd.
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
711 granted / 941 resolved
+7.6% vs TC avg
Moderate +11% lift
Without
With
+11.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
40 currently pending
Career history
999
Total Applications
across all art units

Statute-Specific Performance

§101
2.5%
-37.5% vs TC avg
§103
87.2%
+47.2% vs TC avg
§102
6.0%
-34.0% vs TC avg
§112
3.6%
-36.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 941 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Election/Restrictions Applicant's election with traverse of species A, figs. 6-10, claims 1-16, in the reply filed on 1/25/26 is acknowledged. The traversal is on the ground(s) that “…even assuming arguendo that Species A and Species B are independent or distinct, the examiner does not need to search for the different relationships (i.e., 1:1 or 3:1) between the light source and solder supply.” This is not found persuasive because while the claims may be currently generic to both Species A and Species B, the restriction requirement ensures subsequent amendments to the claims or new claims added during prosecution are directed to the elected species. The requirement is still deemed proper and is therefore made FINAL. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3, 5 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., US Publication No. 2018/0323170 A1 in view of Zakel[1] et al., US Publication No. 2003/0235976 A1. Kim teaches: 1. A method for making a semiconductor device, comprising (see fig. 11): providing a package comprising: a substrate (910) comprising a first substrate surface and a second substrate surface opposite to the first substrate surface; a first conductive bump (981) formed on the first substrate surface; and a first encapsulant (950) disposed on the first substrate surface and encapsulating the first conductive bump (981); forming a groove (955) in the first encapsulant (950) to expose at least a portion of the first conductive bump (981); and forming a second conductive bump (982) on the exposed portion of the first conductive bump (981)… See Kim at para. [0001] – [0200], figs. 1-22. Regarding claim 1: Kim does not expressly teach: The second conductive bump is formed :using a laser soldering apparatus”. In an analogous art, Zakel[1] teaches: (see figs. 1-6) a first conductive bump (31) formed on a first substrate surface (20); and a first encapsulant (32) disposed on the first substrate surface and encapsulating the first conductive bump; forming a groove (34) in the first encapsulant to expose at least a portion of the first conductive bump; and forming a second conductive bump (35) on the exposed portion of the first conductive bump using a laser soldering apparatus (30 in fig. 5). See Zakel[1] at para. [0035] – [0041], Regarding claim 2: Kim further teaches: 2. The method of claim 1, wherein the second conductive bump (982) protrudes outside the groove (955), fig. 11C. Zakel[1] also teaches: 2. The method of claim 1, wherein the second conductive bump (35) protrudes outside the groove (34), fig. 5. Kim further teaches: 3. The method of claim 1, wherein the package further comprising: a first electronic component (970) mounted on the first substrate surface and encapsulated by the first encapsulant (950); a second electronic component (920) mounted on the second substrate surface; and a second encapsulant (940) disposed on the second substrate surface and encapsulating the second electronic component (920), fig. 11C. Kim further teaches: 5. The method of claim 1, wherein forming the groove in the first encapsulant comprises: forming the groove in the first encapsulant using a laser ablation process, para. [0109]. Kim further teaches: 16. A semiconductor device, wherein the semiconductor device is made using the method of claim 1, fig. 11E. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Kim with the teachings of Zakel[1] because “Compared with the known method, the method according to the invention thus has the advantage that as a result of the melting of the joining material moldings using laser energy, locally delimited, exactly definable thermal energy can be produced in the joining material moldings…” See Zakel[1] at para. [0011]. Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Zakel[1], as applied to claim 1 above, in further view of Healy et al., US Publication No. 014/0196940 A1, Regarding claim 4: Kim and Zakel[1] teach all the limitations of claim 1 above, and Kim further teaches the groove (955) exposes a top surface of the first conductive bump (981). Kim does not expressly teach the groove exposes a portion of a lateral surface of the first conductive bump. In an analogous art, Healy teaches: (see fig. 5) a groove (305+308b) exposes a top surface and a portion of a lateral surface of a first conductive bump (306b). See Healy at para. [0058] – [0070], also see fig. 6. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Kim with the teachings of Healy because “…allowing a path to relieve pressure created when moisture gets entrapped in through mold vias, during the manufacturing process, while also reducing the risk of solder shorts between adjacent solder balls located in the through mold vias…As a result, process margins and risks associated with surface mount technology (SMT) may be improved and provide more flexibility on inventory staging.” See Healy at Abstract. Claim(s) 6-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Zakel[1], as applied to claim 1 above, in further view of Zakel[2] et al., "High Speed Laser Solder Jetting Technology for Optoelectronics and MEMS Packaging" (2002): pages 1-7. Regarding claim 6: Kim and Zakel[1] teach all the limitations of claim 1 above, and Zakel[1] further teaches: 6. The method of claim 1, wherein the laser soldering apparatus comprises: a light source configured for irradiating a laser beam, para. [0037]. Kim and Zakel[1] do not expressly teach: a solder supplying component configured for supplying a solder wire. In an analogous art, Zakel[2]teaches: (see fig. 2) a light source (e.g. Nd:YAG laser) configured for irradiating a laser beam; and a solder supplying component (e.g. Singulation Unit) configured for supplying a solder wire. See Zakel[2] at page 3. Regarding claim 7: Zakel[1] further teaches: 7. The method of claim 6, wherein forming the second conductive bump on the exposed portion of the first conductive bump comprises: (see fig. 5) supplying….a predetermined mount of solder (35) onto the exposed portion of the first conductive bump (31); and (see fig. 6) melting, by the light source (30), the predetermined mount of solder to form the second conductive bump (35), para. [0039] – [0041]. Kim and Zakel[1] do not expressly teach “a solder supply component”. Zakel[2] further teaches: supplying, by the solder supplying component (e.g. Singulation Unit), a predetermined mount of solder. See Zakel[2] at page 3. Regarding claim 8: Zakel[1] further teaches: 8. The method of claim 7, further comprising: pre-heating, by the light source (e.g. Nd:YAG laser), the first conductive bump (29 in fig. 1 becomes 31 in fig. 2) to a predetermined temperature, para. [0037]. Regarding claim 9: Zakel[1] further teaches: 9. The method of claim 7, further comprising: post-heating, by the light source (30), the first conductive bump (31) and the second conductive bump (35) to integrate them together, para. [0039], fig. 6. Regarding claim 10: Zakel[1] teaches the limitations as applied to claim 7 above. 10. The method of claim 6, forming the second conductive bump on the exposed portion of the first conductive bump comprises: (see fig. 5) supplying…a predetermined mount of melted solder (35) onto the exposed portion of the first conductive bump (31) to form the second conductive bump, para. [0039]. Kim and Zakel[1] do not expressly teach “a solder supply component”. Zakel[2] further teaches: (see fig. 2) melting, by the pre-heater (e.g. Nd:YAG laser), a portion of the solder wire supplied by the solder supplying component (e.g. Singulation Unit); and supplying, by the solder supplying component, a predetermined mount of melted solder. See Zakel[2] at page 3 Regarding claim 11: Zakel[1] teaches the limitations as applied to claim 8 above. Regarding claim 12: Zakel[1] teaches the limitations as applied to claim 9 above. Regarding claim 13: Zakel[1] teaches the limitations as applied to claim 7 above. Kim and Zakel[1] do not expressly teach “a cutting component”. Zakel[1] further teaches: (see fig. 2) wherein the laser soldering apparatus further comprises a wire cutting component, cutting, by the wire cutting component, a portion of the solder wire supplied by the solder supplying component (e.g. See page 3: “…the Laser Jet is using preformed solder balls which are singulated and jetted via a capillary onto the substrate.) Regarding claim 14: Zakel[1] teaches the limitations as applied to claim 8 above. Regarding claim 15: Zakel[1] teaches the limitations as applied to claim 9 above. t would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Kim with the teachings of Zakel[1] because “Compared with the known method, the method according to the invention thus has the advantage that as a result of the melting of the joining material moldings using laser energy, locally delimited, exactly definable thermal energy can be produced in the joining material moldings…” See Zakel[1] at para. [0011]. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Kim with the teachings of Zakel[2] because “This technology fulfills all the needs of fluxless soldering, local heating and reflow, no mechanical contact and stress during soldering, high solder alloy flexibility and capability of 3D-packaging.” See Zakel[2] at Abstract. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini, can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Michele Fan/ Primary Examiner, Art Unit 2818 29 April 2026
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Prosecution Timeline

Sep 04, 2023
Application Filed
May 07, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
87%
With Interview (+11.2%)
2y 7m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 941 resolved cases by this examiner. Grant probability derived from career allowance rate.

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