DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5, 7-14, 16-18 is/are rejected under 35 U.S.C. 102 (a1) as being anticipated by JP2003-249750A.
Regarding claim 1, JP2003-249750A discloses :a stack comprising at least one electrically conductive layer structure(fig 2d, 13) and at least one electrically insulating layer structure(fig 2d, 11a); wherein a first electrically insulating layer structure of the at least one electrically insulating layer structure has at least partly tapering first through holes filled at least partially with a first electrically conductive filling(fig 2b, A); wherein different ones of the first through holes of the first electrically insulating layer structure are tapering in opposite directions(fig 2B); and wherein the at least one electrically conductive layer structure is connected to the first electrically conductive filling of at least one of the first through holes(fig 2d), wherein the different ones of the first through holes are tapering exclusively within the at least one electrically insulating layer structure(fig 2b, the via’s in structure 11a).
Regarding claim 2, JP2003-249750A discloses : wherein the first electrically conductive filling of at least one of the first through holes comprises at least one of the following: a conductive paste, a nano wire, a sintering material, a conductive sponge, a solder material(states the via is filled with a metal paste, fig2b, 12) .
Regarding claim 3, JP2003-249750A discloses : wherein the at least one electrically conductive layer structure(fig 2d, 13) is connected to the first electrically conductive filling(fig 2d, 12) of at least one of the first through holes by least one of: a conductive paste, nano wires, a sintering material, a conductive sponge a solder material(states the via is filled with a metal paste, fig2b, 12).
Regarding claim 5, JP2003-249750A discloses wherein a second electrically insulating layer structure(fig 2d, 1b) of the at least one electrically insulating layer structure is arranged on the first electrically insulating layer structure(fig 2d, 1a) with the at least one electrically conductive layer structure in between(fig 2d, 13).:
Regarding claim 7, JP2003-249750A discloses herein the second electrically conductive filling(fig 2D, 2) is made of the same material or a different material as the at least one electrically conductive layer structure(fig 2D, 3)(both materials are made of copper see para 0004);
Regarding claim 8, JP2003-249750A discloses wherein the first electrically insulating layer structure and the second electrically insulating layer structure comprise at least one different physical and/or chemical property.(Fig 2d, the second insulating layer 1b does not have via in it where the insulating layer 1a has via’s running through it.).
Regarding claim 9, JP2003-249750A discloses: wherein the first electrically insulating layer structure is a central layer structure in the stack(fig 2d, 1a); wherein the second electrically insulating layer structure is an outer layer of the stack(fig 2d, 1b).
Regarding claim 10, JP2003-249750A discloses wherein the second electrically insulating layer structure comprises a high frequency or high-speed application material(the substrate (fig 2b, 1 is made from a glass ceramic (see the second paragraph after the detailed description for this disclosure) and note Suzuki(US 2018/0166355) states glass substrates help reduce the loss at high frequency regions).
Regarding claim 11, JP2003-249750A discloses: wherein the first through holes are arranged such that a material distribution of the first electrically conductive filling on both opposing main surfaces of the first electrically insulating layer structure is homogeneous(fig 2d, the vias have the same number of vias facing opposite directions evenly spaced apart and all the same size)..
Regarding claim 12, JP2003-249750A discloses wherein the through holes are arranged such that a heat removal capability is substantially the same on both opposing main surfaces of the electrically insulating layer structure(since the vias are a mirror image of each other and have the same surface area on both sides of the insulating layer, the heat removing capabilities will be the same on both sides).
Regarding claim 13, JP2003-249750A discloses wherein the through holes of the electrically insulating layer structure are arranged with alternating tapering directions along a horizontal direction or in a horizontal plane((fig 2d, 2).
Regarding claim 14, JP2003-249750A discloses wherein the first through holes have co-planar ends on both opposing main surfaces of the first electrically insulating layer structure.(fig 2c, 12).
Regarding claim 16, JP2003-249750A discloses wherein a difference of a ratio between an electrically conductive surface area and an entire surface area at the two opposing main surfaces of the electrically insulating layer structure is less than 25%(fig 2d, 2, shows an even number of vias and states that the use the same punch to create the vias with each via having the same dimensions, discussed when discussing fig 2b, note I take this limitation to mean the ratio of the area of the metal to entire surface area is the same on both sides of the substrate but not off by more than 25% ).
Regarding claim 17, JP2003-249750A discloses, since only one of the features is required, the feature disclosed is wherein at least part of the first through holes and/or second through holes have a frustoconical shape(fig 2b, A).
Regarding claim 18, JP2003-249750A discloses, since only one of the features is required, the feature disclosed is a component embedded in or surface-mounted on the stack(fig 2d, 4) and being electrically coupled directly to the electrically conductive filling((fig 2d, 2).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP2003-249750A and further in view of JP2017123424A and further in view of Kasuya et al. (US 2009/0115050)
Regarding claim 4, JP2003-249750A does not disclose wherein the first electrically insulating layer structure comprises fully cured resins having reinforcing agents. However, Kasuya et al. discloses the first electrically insulating layer structure comprises fully cured resins(fig 4, 3; see attached description) and Kasuya et al. discloses reinforcing agents in the substrate(para 0063). It would have been obvious to use fully cured resins having reinforcing agents as shown by JP2017123424A and Kasuya et al. since this is a known durable material and adding the reinforcing material adds strengths to the insulating layer. Additionally, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious engineering choice. In re Leshin, 125 USPQ 416 (CCPA 1960).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP2003-249750A and further in view of Kajihara(US 2017/0309558) .
Regarding claim 6, JP2003-249750A does not disclose the second electrically insulating layer structure has at least partly tapering second through holes filled at least partially with a second electrically conductive filling, wherein different ones of the second through holes are tapering in opposite directions or are tapering all in the same direction. However, Kajihara discloses an interposer with a second electrically insulating layer(fig 1, 130) structure that has through holes filled at least partially with a second electrically conductive filling(fig 1, 136). It would have been obvious to have a second electrically insulating layer structure that has through holes filled at least partially with a second electrically conductive filling.as shown by Kajihara. since this is known to increase the electrical functionality of the interposer. Additionally, it has been held obvious to form the through holes in the second electrically insulating layer with a tapering second through holes, wherein different ones of the second through holes are tapering in opposite directions since this is disclosed by JP2003-249750A so as to prevent warping in the insulating layer.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP2003-249750A and further in view of Kawashita et al. (US 2020/00153363.)
Regarding claim 15, JP2003-249750A does not disclose wherein a thickness of the electrically insulating layer structure is less than 120 um. However, Kawashita et al. discloses wherein a thickness of the electrically insulating layer structure is less than 120 um(para 0022). It would have been obvious to use a thickness of the electrically insulating layer structure is less than 120 um as shown by Kawashita et al. since this is a known thickness providing the strength with a minimal size for the interposer.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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