Prosecution Insights
Last updated: October 02, 2026
Application No. 18/460,760

Support Device for One or More MEMS Components

Final Rejection §103
Filed
Sep 05, 2023
Priority
Sep 28, 2022 — DE 102022210285.1
Examiner
MCDONALD, JASON ANDREW
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Carl Zeiss SMT GmbH
OA Round
2 (Final)
57%
Grant Probability
Moderate
3-4
OA Rounds
6m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 57% of resolved cases
57%
Career Allowance Rate
4 granted / 7 resolved
-10.9% vs TC avg
Strong +80% interview lift
Without
With
+80.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
48 currently pending
Career history
63
Total Applications
across all art units

Statute-Specific Performance

§103
65.2%
+25.2% vs TC avg
§102
20.5%
-19.5% vs TC avg
§112
13.9%
-26.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 7 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claim 15 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7 January 2026. Information Disclosure Statement The Information Disclosure Statement (IDS) submitted on 11 August 2025 has been considered by the examiner and made of record in the application file. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4, 6-11, and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Eid et al (US 20210043573 A1, hereinafter “Eid”), in view of Chia et al (WO 9419594 A1, hereinafter “Chia”). Regarding Claim 1 - Eid discloses a device for supporting one or more MEMS components, comprising a base component (118 [0033] and Fig. 1), an interposer (114 [0054] and Fig. 21), which is integrally bonded to the base component in one or more first connection regions and substantially consists of a second material (e.g. ceramic such as diamond, silicon carbide, or aluminum nitride [0031]) with a second coefficient of expansion α2, and a support substrate (102 [0054] and Fig. 21), which is integrally bonded to the interposer in one or more second connection regions and substantially consists of a third material (e.g. ceramic [0027]) with a third coefficient of expansion α3, wherein the support substrate is configured to support the one or more MEMS components (Considered as 106 [0025] and Fig. 21), and for the coefficients of expansion the following holds true: α1 > α2 > α3, preferably α1 > α2 = α3 (α1, coefficient of expansion for copper, 16-16.7E-6 K-1 > α2, coefficient of expansion for ceramic (diamond: 1.1-1.3E-6 K-1, silicon carbide: 2.77E-6 K-1, aluminum nitride: 5.3E-6 K-1), and α2 = α3 with same second and third material. Coefficients of expansion from: “The Engineering Toolbox”, https://www.engineeringtoolbox.com/linear-expansion-coefficients-d_95.html, accessed 29 April 2026). Eid fails to disclose the base component substantially consists of a first material with a first coefficient of expansion α1. However, discloses the base component substantially consists of a first material with a first coefficient of expansion α1 (copper, Chia page 7, lines 7-8). Chia discloses a heat sink assembly analogous to Eid, for use in cooling microelectronic devices. Chia teaches using copper as the material for the heat sink for the benefit of superior heat dissipation (Chia page 7, lines 8-10). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Eid and Chia to use copper as the heat sink material for the benefit of superior heat dissipation. PNG media_image1.png 494 715 media_image1.png Greyscale PNG media_image2.png 354 605 media_image2.png Greyscale Regarding Claim 2 - Eid modified by Chia discloses all the limitations of claim 1. The combination of Eid and Chia further discloses the base component and the support substrate are on opposite sides of the interposer (Eid Fig. 21). Regarding Claim 3 - Eid modified by Chia discloses all the limitations of claim 1. The combination of Eid and Chia further discloses a first connecting layer between the base component and the interposer (116, Eid [0033] and Fig. 1) and a second connecting layer between the interposer and the support substrate (129, Eid [0054] and Fig. 21). Regarding Claim 4 - Eid modified by Chia discloses all the limitations of claim 1. The combination of Eid and Chia further discloses the base component and the support substrate are in mechanical contact with one another exclusively via the interposer (Eid Fig. 21). Regarding Claim 6 - Eid modified by Chia discloses all the limitations of claim 1. The combination of Eid and Chia further discloses the second material and the third material are identical (e.g. ceramic such as diamond, silicon carbide, or aluminum nitride, Eid [0031] and [0027]). Regarding Claim 7 - Eid modified by Chia discloses all the limitations of claim 1. The combination of Eid and Chia further discloses the first material is or contains a metal, preferably copper (Chia page 7, lines 7-8), and/or the second material is or contains a ceramic (Eid [0031]), and/or the third material is or contains a ceramic (Eid [0027]). Regarding Claim 8 - Eid modified by Chia discloses all the limitations of claim 1. The combination of Eid and Chia further discloses the base component and the interposer are connected to one another exclusively in the one or more first connection regions (Eid annotated Fig. 1) and the interposer and the support substrate are connected to one another exclusively in the one or more second connection regions (Eid annotated Fig. 21). Regarding Claim 9 - Eid modified by Chia discloses all the limitations of claim 1. The combination of Eid and Chia further discloses the first connection region or multiple first connection regions together covers or cover a first area of the interposer and the second connection region or multiple second connection regions together covers or cover a second area of the interposer and the first area is larger and/or is otherwise geometrically more advantageous than the second area (The second area can be the difference of area of two rectangles, while the first area can be just the larger rectangle area, inherently larger than the second area, Eid Figs. 1 and 21), and wherein there is no integrally bonded connection that is not present in one of the connection regions (Eid Figs. 1 and 21). Regarding Claim 10 - Eid modified by Chia discloses all the limitations of claim 1. The combination of Eid and Chia further discloses each of the one or more first connection regions has a different basic area than each of the one or more second connection regions (The second area can be the difference of area of two rectangles, while the first area can be just the larger rectangle area, Eid Figs. 1 and 21), and wherein there is no integrally bonded connection that is not present in one of the connection regions (Eid Figs. 1 and 21). Regarding Claim 11 - Eid modified by Chia discloses all the limitations of claim 1. The combination of Eid and Chia further discloses the plurality, preferably each, of the one or more first connection regions has a larger and/or otherwise geometrically more advantageous basic area than each of the one or more second connection regions (The second area can be the difference of area of two rectangles, while the first area can be just the larger rectangle area, inherently larger than the second area, Eid Figs. 1 and 21), and wherein there is no integrally bonded connection that is not present in one of the connection regions (Eid Figs. 1 and 21). Regarding Claim 13 - Eid modified by Chia discloses all the limitations of claim 1. The combination of Eid and Chia further discloses the one or more MEMS components are disposed on a first side of the support substrate (Eid [0093] and Fig. 21). Regarding Claim 14 - Eid modified by Chia discloses all the limitations of claim 13. The combination of Eid and Chia further discloses an electronic component is disposed on a second side of the support substrate that is different from the first side (Eid Fig. 21), wherein the second side comprises the one or more second connection regions and there is an electrical connection between the electronic component and the one or more MEMS components (conductive pathways, Eid [0027]), wherein the interposer preferably has a cutout which at least partially laterally encloses the electronic component (Eid Fig. 21). Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Eid et al (US 20210043573 A1, hereinafter “Eid”), in view of Chia et al (WO 9419594 A1, hereinafter “Chia”), and further in view of Imamura et al (US 20140197533 A1, hereinafter “Imamura”). Regarding Claim 5 - Eid modified by Chia discloses all the limitations of claim 1. The combination of Eid and Chia fails to disclose the interposer has a polygonal, in particular rectangular, or an oval, in particular circular, basic area, wherein the basic area comprises the first and/or the second connection region. However, Imamura discloses the interposer (32, Imamura [0055-0057] and Figs. 6 and 7) has a polygonal, in particular rectangular, wherein the basic area comprises the second connection region. Imamura discloses a semiconductor device analogous to Eid with a lid as interposer over an electronic component. Imamura teaches using a rectangular interposer over an electronic component for the benefit of stiffening the assembly (Imamura [0100]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Eid and Imamura to use a rectangular interposer over an electronic component for the benefit of stiffening the assembly. PNG media_image3.png 377 583 media_image3.png Greyscale PNG media_image4.png 297 570 media_image4.png Greyscale Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Eid et al (US 20210043573 A1, hereinafter “Eid”), in view of Chia et al (WO 9419594 A1, hereinafter “Chia”), and further in view of Imamura et al (US 20140197533 A1, hereinafter “Imamura”), and further in view of Huang et al (US 20050083658 A1, hereinafter “Huang”). Regarding Claim 12 - Eid modified by Chia discloses all the limitations of claim 1. The combination of Eid and Chia further discloses there is no integrally bonded connection that is not present in one of the connection regions (as seen by cross section in Eid Figs. 1 and 21). The combination of Eid and Chia fails to disclose each of the one or more second connection regions has a rectangular basic area. However, Imamura discloses each of the one or more second connection regions has a rectangular basic area (area of 33 connecting 32 and 21, Imamura [0064] and [0098] and Figs. 6 and 7). Imamura discloses a semiconductor analogous to Eid with a lid as interposer over an electronic component. Imamura teaches using a rectangular interposer over an electronic component for the benefit of stiffening the assembly (Imamura [0100]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Eid and Imamura to use a rectangular interposer over an electronic component for the benefit of stiffening the assembly. The combination of Eid, Chia, and Imamura fails to disclose each of the one or more first connection regions has an oval basic area. However, Huang discloses each of the one or more first connection regions has an oval basic area (3213, Huang [0023] and Fig. 7). Huang discloses a heat dissipating module incorporating a heat sink analogous to Eid. Huang teaches using a round heat sink connection area for the benefit of better heat transfer than using contact strips (Huang [0022]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Eid and Huang to use a round heat sink connection area for the benefit of better heat transfer using contact strips. PNG media_image5.png 477 458 media_image5.png Greyscale Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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Prosecution Timeline

Sep 05, 2023
Application Filed
May 04, 2026
Non-Final Rejection mailed — §103
Aug 31, 2026
Response Filed
Sep 29, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12697688
SEMICONDUCTOR DEVICE MANUFACTURING DEVICE AND MANUFACTURING METHOD
3y 5m to grant Granted Aug 04, 2026
Patent 12666616
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
3y 5m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 2 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
57%
Grant Probability
99%
With Interview (+80.0%)
3y 7m (~6m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 7 resolved cases by this examiner. Grant probability derived from career allowance rate.

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