Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested:
“FinFET device including a plurality of nanostructure channels and methods of formation with continuous polysilicon on diffusion edge (CPODE) process”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 15, 17 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park (US 20220130865).
Regarding claim 15. Fig 2 of Park discloses A semiconductor device, comprising:
a first plurality of nanostructure channels (NW1) over a first mesa region 111/100 that extends above a semiconductor substrate 101,
wherein the first plurality of nanostructure channels are arranged in a direction (DR3) that is perpendicular to the semiconductor substrate;
a second plurality of nanostructure channels (NW2) over a second mesa region 112/100 that extends above the semiconductor substrate,
wherein the second plurality of nanostructure channels are arranged in the direction that is perpendicular to the semiconductor substrate (Fig 2);
a first metal gate structure 121 wrapping around each of the first plurality of nanostructure channels [0041];
a second metal gate structure 131 wrapping around each of the second plurality of nanostructure channels [0077];
a gate isolation structure 120_2 ([0023]: ‘fin-cut gate structure’, thereby isolating each gate) between the first metal gate structure and the second metal gate structure; and
an active region isolation structure 150 between the gate isolation structure and the second metal gate structure,
wherein a dielectric liner (the vertically long 122/124 between 120_2 and 150) of the active region isolation structure is included directly on a sidewall of the gate isolation structure (Fig 2).
Regarding claim 17. Park discloses The semiconductor device of claim 15, further comprising:
another gate isolation structure 130_1 between the active region isolation structure and the second metal gate structure (the vertically 132/134 between 130_1 and 150).
Regarding claim 20. Park discloses The semiconductor device of claim 15, wherein the dielectric liner is between a dielectric layer 150 [0085] of the active region isolation structure and the gate isolation structure (Fig 2).
Allowable Subject Matter
Claims 1-14 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1. Park (US 20220130865) discloses some steps of the claimed method including A method, comprising:
forming, over a semiconductor substrate 100, a plurality of nanostructure layers 10 in a direction (DR3) that is perpendicular to the semiconductor substrate (Fig 11),
wherein the plurality of nanostructure layers comprises a plurality of sacrificial layers 12 alternating with a plurality of channel layers 11;
forming, over the plurality of nanostructure layers, a dummy gate structure 120D/130D (Fig 14);
removing portions of the plurality of nanostructure layers to form one or more recesses (R) adjacent to one or more sides of the dummy gate structure (Fig 15);
forming one or more source/drain regions 141/142 in the one or more recesses (Fig 16);
replacing, after forming the one or more source/drain regions, the dummy gate structure and portions of the sacrificial layers under the dummy gate structure with a metal gate structure 121/131 (Fig 17 - Fig 18),
wherein the metal gate structure wraps around at least three sides of the channel layers [0046]/[0077], and
forming an active region isolation structure 150 in the active region isolation recess (Fig 18).
Furthermore, Yang (US 20220173097) discloses similar steps of forming an active region isolation structure (Fig 14C: F1/F2 with NSS) in the active region isolation recess (CTS). Thereby forming step of isolation structure 550C between metal gates (Fig 26F).
However, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, in particular, the required specific order of steps of active region isolation structure, “removing, to form an active region isolation recess after replacing the dummy gate structure and the portions of the sacrificial layers under the dummy gate structure with the metal gate structure:
a portion of the metal gate structure,
portions of the channel layers around which the metal gate structure wraps, and a mesa region, under the portions of the channel layers, that extends above the semiconductor substrate”.
Regarding claim 8. Jo (US 20240178274) discloses some steps of the claimed method including A method, comprising:
forming, over a semiconductor substrate 102, a plurality of nanostructure layers (NS) in a direction (Z) that is perpendicular to the semiconductor substrate (Fig 12C),
wherein the plurality of nanostructure layers comprises a plurality of sacrificial layers 104 alternating with a plurality of channel layers (NS) (Fig 12C);
forming, over the plurality of nanostructure layers, a plurality of dummy gate structures (Fig 13A, [0097]: DGS);
removing portions of the plurality of nanostructure layers to form one or more recesses (R1) adjacent to one or more sides of a dummy gate structure of the plurality of dummy gate structures (Fig 13B);
forming one or more source/drain regions (SD1) in the one or more recesses (Fig 13B);
replacing, after forming the one or more source/drain regions, the plurality of dummy gate structures (Fig 14B) and portions of the sacrificial layers under the plurality of dummy gate structures with a plurality of metal gate structures 160 (Fig 16A),
wherein the plurality of metal gate structures wraps around the channel layers (Fig 16A);
forming gate isolation structures 150 across the plurality of metal gate structures after replacing the dummy gate structure and the portions of the sacrificial layers under the dummy gate structure with the metal gate structure (Fig 16A).
Furthermore, Park (US 20220130865) discloses forming an active region isolation structure 150 in the active region isolation recess between the gate isolation structures (Fig 18).
However, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, in particular, the required specific order of steps of active region isolation structure, “removing, between the gate isolation structures to form an active region isolation recess:
a portion of a metal gate structure of the plurality of metal gate structures,
portions of the channel layers around which the metal gate structure wraps, and
a mesa region, under the portions of the channel layers, that extends above the semiconductor substrate”.
Claims 16 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 16. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the first metal gate structure is in direct contact with another sidewall of the gate isolation structure”.
Regarding claim 18. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the second metal gate structure is in direct contact with a sidewall of the other gate isolation structure”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812