DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/15/2023 and 01/08/2024 have been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tong (US 2011/0067803).
Regarding claim 1, Tong teaches a method of forming a bonded structure, the method comprising:
polishing a surface (33) of a first element (30) to form a polished surface (34);
roughening at least a portion of the polished surface of the first element to form a bonding surface having a roughened surface with a surface roughness of at least 10 A rms (refer to VSE process to the surface 34 wherein the VSE means that a RMS of the slightly etched surface remains at approximately an unetched value in a range of 0.1 nm to 3 nm in pars. 24,43,45,53); and directly bonding the bonding surface of the first element to a bonding surface of a second element (see pars. 24,43,45,53 and figs. 3A-3E).
Claims 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fountain (US 2019/0096842).
Regarding claim 16, Fountain a method of forming a bonding surface for direct bonding, the method comprising:
providing an element (refer to a wafer/substrate) having a polished surface including a non-conductive field region (refer to dielectric layer formed over the substrate) and a conductive feature (refer to conductive material formed in an opening of the dielectric layer) (NOTE: refer to the polished surface of the wafer after polishing the conductive material to expose the barrier layer) ; and
roughening at least a portion of non-conductive field region of the polished surface (NOTE: the step of removing the barrier layer to expose the non-conductive layer with a roughen surface in claim 1).
Regarding claim 17, Fountain teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fountain teaches polishing a surface of the element to form the polished surface (see fig. 5 and claim 1).
Regarding claim 18, Fountain teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fountain teaches the polished surface has a surface roughness of 6 Å rms or less (see claim 1)
Regarding claim 19, Fountain teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fountain teaches roughening the portion of the non- conductive field region comprises forming a roughened surface having a surface roughness greater than 6 Å rms (see claim 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Fountain (US 20190096742), and further in view of Sadaka (US 20120313237).
Regarding claim 1, Fountain teaches a method of forming a bonded structure, the method comprising:
polishing a surface of a first element to form a polished surface (refer to step polishing at least a portion of the conductive structure to reveal a surface of the barrier layer) (see steps 1108 in par. 121 or claim 1);
roughening at least a portion of the polished surface of the first element to form a bonding surface having a roughened surface with a surface roughness of less than 10 Å rms (refer to the step of removing the barrier layer to reveal a planar dielectric bonding surface with a surface roughness of less than 1 nm root mean square (RMS) in par. 22); and
directly bonding the bonding surface of the first element to a bonding surface of a second element (see par. 22 and fig. 5).
Fountain does not explicitly teach the bonding surface having a roughened surface with a surface roughness of at least 10 Å rms.
Sadaka teaches the same field of an endeavor wherein a roughness of the bonding surface’s range less than about 100 Å rms (see par. 42).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the bonding surface having a roughened surface with a surface roughness of at least 10 Å rms as taught by Sadaka in the teaching of Fountain in order to improve the smoothness and planarity of the surface of a processed semiconductor structure in order to allow attachment of a semiconductor structure to the processed semiconductor structure (see par. 29).
Regarding claim 2, Fountain and Sadaka teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fountain teaches the first element (refer to wafer 102) comprises a non-conductive field (refer to dielectric layer 502) and a conductive feature at the bonding surface (504) (see par. 58 and fig. 5).
Regarding claim 3, Fountain and Sadaka teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fountain teaches polishing the surface comprises polishing the non-conductive field region to a surface roughness of 6 Å rms or less (see par. 22).
Regarding claim 4, Fountain and Sadaka teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fountain teaches roughening a portion of the non-conductive field region (refer to planar dielectric bonding surface) to a surface roughness at least 20 Å rms (see par. 22).
Regarding claim 5, Fountain and Sadaka teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fountain teaches the entire polished surface of the non- conducive field region is roughened (see par. 22).
Regarding claim 6, Fountain and Sadaka teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fountain teaches the second element (refer to upper wafer) comprises a non- conductive field region (506) and a conductive feature (508), wherein the non-conductive field region of the first element and the non-conductive field region of the second element are directly bonded to one another without an intervening adhesive (see fig. 5 and par. 22).
Regarding claim 7, Fountain and Sadaka teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fountain teaches the conducive feature of the first element and the conductive feature of the second element are directly bonded to one another without an intervening adhesive (see fig. 5).
Regarding claim 8, Fountain and Sadaka teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fountain teaches polishing a surface of the second element to define the bonding surface of the second element (see par. 58).
Regarding claim 9, Fountain and Sadaka teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fountain teaches polishing a surface of the second element to define a polished surface of the second element, and roughening at least a portion of the polished surface of the second element to define the bonding surface of the second element that includes a roughened surface.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Fountain (US 20190096742) as applied to claim 16 above, and further in view of Sadaka (US 20120313237).
Regarding claim 20, Fountain teaches all the limitations of the claimed invention for the same reasons as set forth above except for the surface roughness of the roughened surface is in a range of 35 Å rms to 200 Å rms.
Sadaka teaches the same field of an endeavor wherein a roughness of the bonding surface’s range less than about 100 Å rms (see par. 42).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the surface roughness of the roughened surface is in a range of 35 Å rms to 200 Å rms as taught by Sadaka in the teaching of Fountain in order to improve the smoothness and planarity of the surface of a processed semiconductor structure in order to allow attachment of a semiconductor structure to the processed semiconductor structure (see par. 29).
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “roughening the portion of the polished surface comprises patterning a masking structure over the polished surface”. Claims 11-15 include all of the limitations of claim 10.
Claim 21 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “patterning a masking structure over the polished surface before roughening”. Claims 22-24 include all of the limitations of claim 21.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Niki Tram Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-4:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIKI H NGUYEN/ Primary Examiner, Art Unit 2818