DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 12/26/2025 is acknowledged.
Claims 15-20 are cancelled pursuant to applicant’s amendment filed on 12/26/2025. Election was made without traverse in the reply filed on 12/26/2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US-20220367401-A1 – hereinafter Kim).
Regarding claim 1, Kim teaches a semiconductor package (Fig.1A 1000A; ¶0016), comprising:
a semiconductor die (Fig.1A 200; ¶0017) comprising die connectors (Fig.1A 204 and 220; ¶0030);
a first insulating encapsulant (Fig.1A 400; ¶0017) laterally covering the semiconductor die (200);
a die attach film (DAF) (Fig.1A 300a; ¶0017) overlying the first insulating encapsulant (400) and the semiconductor die (200), the die connectors (204 and 220) being laterally covered by the DAF (300a); and
a redistribution structure (Fig.1A 100; ¶0017) overlying the DAF (300a) and the semiconductor die (200), the redistribution structure (100) being electrically coupled to the die connectors (204 and 220).
Regarding claim 2, Kim teaches the semiconductor package of claim 1, wherein surfaces of the DAF (300a) and the die connectors (204 and 220) are substantially leveled (these components are coplanar at the bottom surface of 200).
Regarding claim 3, Kim teaches the semiconductor package of claim 1, wherein a portion of the DAF (300a) extends to cover at least a portion of a sidewall of the semiconductor die (200).
Regarding claim 4, Kim teaches the semiconductor package of claim 1, wherein sidewalls of the DAF (300a) and the first insulating encapsulant (400) are substantially leveled (both components have a coplanar surface in Fig.1A).
Regarding claim 6, Kim teaches the semiconductor package of claim 1, wherein a viscosity (lower viscosity of 300a discussed in ¶0080) of the DAF (300a) is lower than that of the first insulating encapsulant (400).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 8 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim.
Regarding claim 8, Kim teaches the semiconductor package of claim 1, further comprising:
an interposer (Fig.4 600; ¶0052) disposed on and electrically coupled to the redistribution structure (100).
Kim does not teach a second insulating encapsulant disposed on the redistribution structure and laterally covering the interposer.
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to encapsulate the interposer (600) with an encapsulant like that of the first insulating encapsulant (400) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of protecting the interposer (600) from the external environment.
Regarding claim 10, Kim teaches the semiconductor package of claim 8, wherein the interposer (600) is electrically coupled (¶0025) to the redistribution structure (100) through solder joints (Fig.1A 120; ¶0025).
Claim(s) 5, 21 and 23-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chang et al. (US-20200303316-A1 – hereinafter Chang).
Regarding claim 5, Kim teaches the semiconductor package of claim 1, wherein the semiconductor die (200) further comprises a dielectric layer (Fig.1A 210; ¶0028), and an adhesive strength of the DAF with respect to the die connectors is greater than that of the dielectric layer with respect to the die connectors.
Kim does not explicitly teach the dielectric layer laterally covering via portions of the die connectors.
Chang teaches a semiconductor die (Fig.1H 28; ¶0025 of Chang) having connectors (Fig.1H 23 and 25; ¶0025 of Chang) with first portions (23 of Chang) and second portions (25 of Chang), the first portions (23 of Chang) being covered by a dielectric layer (Fig.1H 24; ¶0025 of Chang) and the second portions (25 of Chang) overlying the dielectric layer (24 of Chang).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the semiconductor die of Kim (200 of Kim) to have a design like the semiconductor die taught by Chang (28 of Chang) with the die connectors (204 and 220 of Kim) being partially covered by the dielectric layer (210 of Kim) in the lateral direction to arrive at the claimed invention. This change is obvious because it is well-known in the art and a matter of design choice.
Regarding claim 21, Kim teaches a semiconductor package (Fig.1A 1000A; ¶0016), comprising:
a semiconductor die (Fig.1A 200; ¶0017) comprising a dielectric layer (Fig.1A 210; ¶0028) and die connectors (Fig.1A 204 and 220; ¶0030), the die connectors (204 and 220) comprising second portions overlying (204 and 220 are depicted entirely overlying the bottom of 210) a first surface (bottom surface of 210) of the dielectric layer (210);
an insulating encapsulant (Fig.1A 400; ¶0017) surrounding the semiconductor die (200);
an adhesive layer (Fig.1A 300a; ¶0017) surrounding the die connectors (204 and 220), wherein a first surface (bottom surface) of the adhesive layer (300a) is substantially leveled with surfaces of the die connectors (bottom of 204 and 220), and a second surface (top surface) of the adhesive layer (300a) opposite to the first surface (bottom surface) is interfaced with the first surface (bottom surface) of the dielectric layer (210) and a surface of the insulating encapsulant (400); and
a redistribution structure (Fig.1A 100; ¶0017) disposed on the first surface (bottom surface) of the adhesive layer (300a) and the surfaces of the die connectors (204 and 220).
Kim does not teach the die connectors comprising first portions laterally covered by the dielectric layer and connected to the second portions.
Chang teaches a semiconductor die (Fig.1H 28; ¶0025 of Chang) having connectors (Fig.1H 23 and 25; ¶0025 of Chang) with first portions (23 of Chang) and second portions (25 of Chang), the first portions (23 of Chang) being covered by a dielectric layer (Fig.1H 24; ¶0025 of Chang) and the second portions (25 of Chang) overlying the dielectric layer (24 of Chang).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the semiconductor die of Kim (200 of Kim) to have a design like the semiconductor die taught by Chang (28 of Chang) with the die connectors (204 and 220 of Kim) being partially covered by the dielectric layer (210 of Kim) in the lateral direction to arrive at the claimed invention. This change is obvious because it is well-known in the art and a matter of design choice.
Regarding claim 23, the aforementioned combination of Kim in view of Chang from claim 21 teaches the semiconductor package of claim 21, wherein:
the semiconductor die (200 of Kim) further comprises a semiconductor substrate (Fig.1A 201; ¶0027 of Kim), and the dielectric layer (210 of Kim) and the die connectors (204 and 220 of Kim) are disposed over the semiconductor substrate (201 of Kim), and a thickness of the adhesive layer (300a of Kim) on a sidewall of the semiconductor die (200 of Kim) decreases in a direction from the dielectric layer (210 of Kim) toward the semiconductor substrate (201 of Kim).
Regarding claim 24, the aforementioned combination of Kim in view of Chang from claim 21 teaches the semiconductor package of claim 21, wherein an adhesive strength of the adhesive layer (300a of Kim) with respect to the die connectors (204 and 220 of Kim) is greater (it is presumed that an adhesive layer has a higher strength then a dielectric layer) than an adhesive strength of the dielectric layer (210 of Kim) with respect to the die connectors (204 and 220 of Kim).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Kawasaki et al. (US-20150069596-A1 – hereinafter Kawasaki).
Regarding claim 7, Kim teaches the semiconductor package of claim 1.
Kim does not teach wherein a density of fillers of the DAF is lower than a density of fillers of the first insulating encapsulant.
Kawasaki teaches silica fillers present in both an underfill resin and an encapsulant resin, where the density of fillers in the underfill resin is lower than a density of fillers in the encapsulant resin (¶0028 of Kawasaki).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the silica fillers of Kawasaki (¶0028 of Kawasaki) in the adhesive (300a of Kim) and insulating encapsulant (400 of Kim) in the same relative densities (¶0028 of Kawasaki) to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for the benefit of the adhesive (300a of Kim) having less viscosity than the encapsulant (400 of Kim) and to be easily and smoothly filled (¶0028 of Kawasaki) between the die (200 of Kim) and the redistribution structure (100 of Kim).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chan et al. (US-20140084455-A1 – hereinafter Chan).
Regarding claim 9, Kim teaches the semiconductor package of claim 8.
Kim does not teach wherein sidewalls of the DAF, the first insulating encapsulant, and the second insulating encapsulant are substantially leveled.
Chan teaches an adhesive layer (Fig.2H 23; ¶0036 of Chan) that is flush with an encapsulating layer (Fig.2H 24; ¶0036 of Chan) at the sidewalls (¶0036 of Chan).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the package design of the package taught by Kim (1000A of Kim) so the adhesive (300a of Kim) and insulating encapsulants (400 of Kim) are flush at the sides as taught by Chan (Fig.2H of Chan) to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for the benefit of strengthening the adhesion of the insulating encapsulant (400 of Kim) to the redistribution structure (100 of Kim) by providing more surface area interfacing with the adhesive layer (300a of Kim).
Claim(s) 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Tsao et al. (US-20240178159-A1 – hereinafter Tsao).
Regarding claim 11, Kim teaches a semiconductor package (Fig.1A 1000A; ¶0016), comprising:
a first semiconductor die (Fig.1A 200; ¶0017);
a first insulating encapsulant (Fig.1A 400; ¶0017) laterally surrounding the first semiconductor die (200);
an adhesive layer (Fig.1A 300a; ¶0017) disposed on the first insulating encapsulant (400) and the first semiconductor die (200), where an active surface (bottom surface) of the first semiconductor die (200) is substantially leveled with a top surface of the adhesive layer (300a); and
a redistribution structure (Fig.1A 100; ¶0017) disposed on the adhesive layer (300a) and the active surface (bottom surface) of the first semiconductor die (200), the redistribution structure (100) being electrically coupled to the first semiconductor die (200).
Kim does not teach wherein a rear surface of the first semiconductor die opposite to the active surface is substantially leveled with a bottom surface of the first insulating encapsulant.
Tsao teaches a semiconductor die (Fig.1 101; ¶0031 of Tsao) with a rear surface (Fig.1 101b; ¶0032 of Tsao) that is level with an encapsulant (Fig.1 110; ¶0032 of Tsao).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the semiconductor package of Kim (1000A of Kim) so the top surface of the semiconductor die (200 of Kim) is flush with the top surface of the insulating encapsulant (400 of Kim) as taught by Tsao (Fig.1 of Tsao) to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for the benefit of increased heat dissipation off the top surface of the semiconductor die (200 of Kim).
Regarding claim 12, the aforementioned combination of Kim in view of Tsao from claim 11 teaches the semiconductor package of claim 11, wherein at least a portion of the adhesive layer (300a of Kim) extends to cover a sidewall of the first semiconductor die (200 of Kim) that is connected to the rear surface (top of 200 of Kim).
Regarding claim 13, the aforementioned combination of Kim in view of Tsao from claim 11 teaches the semiconductor package of claim 11, wherein the first semiconductor die (200 of Kim) comprises die connectors (Fig.1A 204 and 220; ¶0030 of Kim) at the active surface (bottom surface of 200 of Kim), and the adhesive layer (300a of Kim) laterally covers each of the die connectors (204 and 220 of Kim).
Regarding claim 14, the aforementioned combination of Kim in view of Tsao from claim 11 teaches the semiconductor package of claim 11, further comprising:
a second semiconductor die (Fig.4 600; ¶0052 of Kim) disposed on and electrically coupled to the redistribution structure (100 of Kim).
The aforementioned combination does not teach a second insulating encapsulant disposed on the redistribution structure and encapsulating the second semiconductor die.
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to encapsulate the interposer (600 of Kim) with an encapsulant like that of the first insulating encapsulant (400 of Kim) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of protecting the interposer (600 of Kim) from the external environment.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chang, and further in view of Kuo et al. (US-20220278069-A1 – hereinafter Kuo).
Regarding claim 22, the aforementioned combination of Kim in view of Chang from claim 21 teaches the semiconductor package of claim 21.
The aforementioned combination does not teach wherein an interface of the surface of the insulating encapsulant and a portion of the second surface of the adhesive layer extending to a sidewall of the semiconductor die is a curve surface.
Kuo teaches an adhesive layer (Fig.1D 114; ¶0032) with a curved surface.
Shape differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. Additionally, the Applicant has presented no discussion in the specification which convinces the Examiner that the particular shape of the adhesive layer is anything more than one of numerous shapes a person of ordinary skill in the art would find obvious for the purpose of adhering the semiconductor die to the redistribution structure (In re Dailey, 149 USPQ 47 (CCPA 1976)). It appears that these changes produce no functional differences and therefore would have been obvious.
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chang, and further in view of Kawasaki.
Regarding claim 25, the aforementioned combination of Kim in view of Chang from claim 21 teaches the semiconductor package of claim 21.
The aforementioned combination does not teach wherein the adhesive layer comprises first fillers, the insulating encapsulant comprises second fillers, and a density of the first fillers of the adhesive layer is less than a density of the second fillers of the insulating encapsulant.
Kawasaki teaches silica fillers present in both an underfill resin and an encapsulant resin, where the density of fillers in the underfill resin is lower than a density of fillers in the encapsulant resin (¶0028 of Kawasaki).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the silica fillers of Kawasaki (¶0028 of Kawasaki) in the adhesive (300a of Kim) and insulating encapsulant (400 of Kim) in the same relative densities (¶0028 of Kawasaki) to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for the benefit of the adhesive (300a of Kim) having less viscosity than the encapsulant (400 of Kim) and to be easily and smoothly filled (¶0028 of Kawasaki) between the die (200 of Kim) and the redistribution structure (100 of Kim).
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chang, and further in view of Chan.
Regarding claim 26, the aforementioned combination of Kim in view of Chang from claim 21 teaches the semiconductor package of claim 21.
The aforementioned combination does not teach wherein an outer sidewall of the adhesive layer is substantially coplanar with an outer sidewall of the insulating encapsulant.
Chan teaches an adhesive layer (Fig.2H 23; ¶0036 of Chan) that is flush with an encapsulating layer (Fig.2H 24; ¶0036 of Chan) at the sidewalls (¶0036 of Chan).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the package design of the package taught by Kim (1000A of Kim) so the adhesive (300a of Kim) and insulating encapsulants (400 of Kim) are flush at the sides as taught by Chan (Fig.2H of Chan) to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for the benefit of strengthening the adhesion of the insulating encapsulant (400 of Kim) to the redistribution structure (100 of Kim) by providing more surface area interfacing with the adhesive layer (300a of Kim).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. (US-20240021493-A1 and US-20240014166-A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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/T.J.K./ Examiner, Art Unit 2817
/RATISHA MEHTA/ Primary Examiner, Art Unit 2817