Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I in the reply filed on 03/10/2026 is acknowledged. Claims 1-10, 15, 17-25, 29, 33-35, 37-40 and 82 are examined below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10, 15, 17-25, 29, 33-35, 37-39, 82 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites, “…source fingers configured to extend from the at least one drain pad longitudinally toward the central location of the transistor die…”. It is unclear what the relationship is required between the source fingers and drain pad. For example, it is unclear where the claim requires the source fingers to be electrically connected to the drain pad, to physically originate from the drain pad, or merely to be positioned on the drain pad side region of the transistor die. For the purpose of examination, this limitation is interpreted as source fingers are positioned in, and extended from the drain-side region toward the center active finger region, and does not require that the source fingers be electrically common with the drain pad itself.
Claim 1 further recites, “…the gate is configured to extend along implementations of the drain fingers and/or the source fingers…”, which is unclear. In particular, the term “implementations” does not identify a reasonably clear structure in this context, and the phrase “extended along” does not make clear the required positional relation between the gate and the drain fingers and/or source fingers. Thus, it is uncertain whether the claim requires the gate to extend parallel, adjacent to, over, between, or otherwise relative to the drain fingers and/or source fingers. For the purpose of examination, this limitation is interpreted as requiring that the gate extend generally with the drain-finger and/or source finger array in the longitudinal direction of that array, without requiring a specific positional relationship such as parallel to, directly adjacent to, over, or between the drain fingers and/or source fingers.
Claim 1 further recites, “…gate pad is arranged on an axis at least semi-orthogonally to an axis of the at least one drain pad”. It is unclear what degree of angular relationship is required by “semi-Orthogonal”. For example, it is unclear whether “semi-orthogonal” encompasses axes that are exactly orthogonal, approximately orthogonal, or some broader range of angular offsets from orthogonal. For the purpose of examination, this limitation is interpreted as orthogonal or approximately orthogonal arrangements.
Claim 82 is also indefinite for the same reason as claim 1 regarding “semi-orthogonal”, hence rejected under 35 U.S.C. 112(b).
Claims 2-10, 15, 17-25, 29, 33-35, 37-39 inherit the indefiniteness of claim 1, hence rejected under 35 U.S.C. 112(b).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5-10, 40, 82 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Jeon (US 20180026123 A1).
PNG
media_image1.png
258
551
media_image1.png
Greyscale
Re: Independent Claim 1, Jeon discloses a transistor die comprising:
at least one drain pad arranged at a first die side of the transistor die and/or at a second die side of the transistor die, the first die side and the second die side being opposed sides of the transistor die (Jeon teaches, in Fig. 8A and ¶ [0068], semiconductor device 82 having at least one drain pad 91 positioned over the longer group of cells/fingers 88, and drain pad 91 is at the first side as annotated in the fig. 8A(annotated), and second drain pad 92 on second side as annotated in the fig. 8A(annotated) positioned opposite drain pad 91);
drain fingers configured to extend from the at least one drain pad longitudinally toward a central location of the transistor die (Jeon teaches, in Fig. 9A-9C and ¶ [0070], drain finger 128 is extending from drain pads 91 and 92 respectively towards the central location of 82);
source fingers configured to extend from the at least one drain pad longitudinally toward the central location of the transistor die (Jeon teaches, in Fig. 9B, source finger 132 in the same finger field as drain finger 128 and gate 130, and Fig. 9A and 9C show that finger field positioned beneath/inward of drain-pad region 120/124. Thus, source finger 132 is positioned in, and extends inward from, drain-pad-side-region towards the central active region); and
a gate pad and a gate and the gate is configured to extend along implementations of the drain fingers and/or the source fingers (Jeon, in Figs. 8A and 9A-9C, teaches gate pad 96, gate 130 adjacent source finger 132 and within the finger field; and the gate 130 is arranged to extend along the finger array including drain finger 128 and source finger 132),
wherein the gate pad is arranged on an axis at least semi-orthogonally to an axis of the at least one drain pad (gate pad 96 relative to drain pad 91 is at least semi-orthogonal, consistent with the instant application’s axis-based definition of “semi-orthogonally”).
Re: Claim 5, Jeon discloses all the limitations of claim 1 on which this claim depends.
Jeon further discloses,
wherein the drain fingers comprise multiple parallel implementations extending laterally across the transistor die; and wherein the source fingers comprise multiple parallel implementations extending laterally across the transistor die (Jeon teaches, in ¶ [0023], that the active area includes a plurality of source fingers and plurality of drain fingers interdigitated with one another. Jeon further teaches, in Figs. 8A and 9A-9C, drain fingers 128 and source fingers 132 comprise multiple parallel implementations extending laterally across the transistor die).
Re: Claim 6, Jeon discloses all the limitations of claim 1 on which this claim depends.
Jeon further discloses,
wherein the drain fingers comprises a dimension longitudinally along the transistor die greater than a dimension extending laterally across the transistor die; and wherein the source fingers have a dimension longitudinally along the transistor die greater than a dimension extending laterally across the transistor die (Jeon teaches semiconductor device having plurality of fingers, including drain finger 128 and source finger 132, in the active finger field of semiconductor device 82, with the drain pads coupled to the finger field through drain feed 126 and contacts 136. As reasonably shown in Figs. 9A-9C, and particularly Fig. 9B, drain finger 128 and source finger 132 each extend in a direction having a greater longitudinal dimension than lateral width. Jeon also explain, in ¶ [0067], that the BOA structure may be implemented using “longer fingers”, because longer fingers help improve the aspect ratio of the device, which further supports a finger geometry having greater longitudinal than lateral dimension).
PNG
media_image2.png
277
551
media_image2.png
Greyscale
Re: Claim 7, Jeon discloses all the limitations of claim 1 on which this claim depends.
Jeon further teaches,
wherein the at least one drain pad are configured to provide an output from a third die side, wherein the third die side is connected to the first die side and the second die side (Jeon, in Fig. 8C teaches the drain pad 112 may be packaged with wires 116, which provides an output. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement this teaching of output provided from drain pad of Fig. 8C in the Annotated Fig. 8A (Annotated1) of Jeon as shown above such that the drain pad 91 will be configured to provide an output, which will be located at a third side as shown in Fig. 8A (Annotated1) above).
PNG
media_image3.png
277
551
media_image3.png
Greyscale
Re: Claim 8, Jeon discloses all the limitations of claim 1 on which this claim depends.
Jeon further teaches,
wherein the at least one drain pad are configured to provide an output from a fourth die side, wherein the fourth die side is connected to the first die side and the second die side (Jeon, in Fig. 8C teaches the drain pad 112 may be packaged with wires 116, which provides an output. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement this teaching of output provided from drain pad of Fig. 8C in the Annotated Fig. 8A (Annotated2) of Jeon as shown above such that the drain pad 91 will be configured to provide an output, which will be located at a fourth side as shown in the Fig. 8A (Annotated2) above).
Re: Claim 9, Jeon discloses all the limitations of claim 1 on which this claim depends.
Jeon further discloses,
wherein the gate pad is configured to extend longitudinally along the transistor die; and wherein the at least one drain pad are configured to extend laterally across the transistor die (Jeon teaches, in Fig. 8A, gate pad 96 extends longitudinally along the die and drain pad 91 extends laterally across the transistor die).
Re: Claim 10, Jeon discloses all the limitations of claim 1 on which this claim depends.
Jeon further discloses,
wherein the at least one drain pad comprises drain pads; and wherein the drain fingers and the source fingers are arranged between the drain pads (Jeon, in Fig. 8A, teaches two drain pads 91 and 92 and group of cells/fingers 88 and 86 arranged between them, and further teaches, in enlarged Fig. 9A, drain fingers 128 and source fingers 132 are arranged between drain pads 120 and 124).
Re: Independent Claim 40, Jeon discloses a transistor die comprising:
drain pads arranged at a first die side of the transistor die and at a second die side of the transistor die, the first die side and the second die side being opposed sides of the transistor die (Jeon teaches, in Fig. 8A and ¶ [0068], semiconductor device 82 having at least one drain pad 91 positioned over the longer group of cells/fingers 88, and drain pad 91 is at the first side as annotated in the fig. 8A(annotated), and second drain pad 92 on second side as annotated in the fig. 8A(annotated) positioned opposite drain pad 91);
drain fingers arranged at the first die side of the transistor die and the second die side of the transistor die (Jeon teaches, in Fig. 9A-9C and ¶ [0070], drain finger 128 is extending from drain pads 91 and 92);
source fingers arranged at the first die side of the transistor die and a second die side of the transistor die (Jeon teaches, in Fig. 9B, source finger 132 in the same finger field as drain finger 128 and gate 130, and Fig. 9A and 9C show that finger field positioned beneath/inward of drain-pad region 120/124. Thus, source finger 132 is positioned in drain-pad-side-region); and
a gate pad and a gate and the gate configured to extend along implementations of the drain fingers and/or the source fingers on the first die side and implementations of the drain fingers and/or the source fingers on the second die side (Jeon, in Figs. 8A and 9A-9C, teaches gate pad 96, gate 130 adjacent source finger 132 and within the finger field; and the gate 130 is arranged to extend along the finger array including drain finger 128 and source finger 132 on both sides of the die).
Re: Independent Claim 82, Jeon discloses a process of implementing a transistor die comprising:
arranging at least one drain pad at a first die side of the transistor die and/or at a second die side of the transistor die, the first die side and the second die side being opposed sides of the transistor die (Jeon teaches, in Fig. 8A and ¶ [0068], semiconductor device 82 having at least one drain pad 91 positioned over the longer group of cells/fingers 88, and drain pad 91 is at the first side as annotated in the fig. 8A(annotated), and second drain pad 92 on second side as annotated in the fig. 8A(annotated) positioned opposite drain pad 91);
configuring drain fingers to extend from the at least one drain pad longitudinally toward a central location of the transistor die (Jeon teaches, in Fig. 9A-9C and ¶ [0070], configuring drain finger 128 such that it is extending from drain pads 91 and 92 respectively towards the central location of 82);
configuring source fingers to extend from the at least one drain pad longitudinally toward the central location of the transistor die (Jeon teaches, in Fig. 9B, source finger 132 in the same finger field as drain finger 128 and gate 130, and Fig. 9A and 9C show that finger field positioned beneath/inward of drain-pad region 120/124. Thus, source finger 132 is positioned in, and extends inward from, drain-pad-side-region towards the central active region);
arranging a gate pad on an axis at least semi-orthogonally to an axis of the at least one drain pad (Jeon, in Figs. 8A and 9A-9C, gate pad 96 relative to drain pad 91 is at least semi-orthogonal, consistent with the instant application’s axis-based definition of “semi-orthogonally”); and
configuring a gate to extend along implementations of the drain fingers and/or the source fingers (Jeon, in Figs. 8A and 9A-9C, teaches gate 130 adjacent source finger 132 and within the finger field; and the gate 130 is arranged to extend along the finger array including drain finger 128 and source finger 132).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20180026123 A1).
Re: Claim 2, Jeon discloses all the limitations of claim 1 on which this claim depends.
Jeon further discloses,
wherein an output from the transistor die from the at least one drain pad is arranged on an axis at least semi-orthogonally to an axis of an input to the gate pad (Jeon teaches, in Fig. 8C, a semiconductor package in which drain pad 112 and gate pad 114 may each be packaged with wires 116 and 118. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the drain-side output connection arrangement and gate-side input connection arrangement shown in the package implementation of Fig. 8C with the pad-orientation layout shown in Fig. 8A and explained in claim 1 rejection above, because Jeon expressly teaches these as different implementations of semiconductor devices having multi-source BOA pads, and doing so would have predictably provide a package ready drain output path and gate input path corresponding to the disclosed die-level pad layout, i.e., applying the known package interconnect arrangement of drain pad 112/wire 116 and gate pad 114/wire 118 to the disclosed pad orientation of drain pad 91 and gate pad 96 would have been an obvious packaging/interconnect optimization within the teaching of Jeon).
Re: Claim 3, Jeon discloses all the limitations of claim 1 on which this claim depends.
Jeon further discloses,
wherein the at least one drain pad comprise a dimension extending laterally across the transistor die greater than a dimension longitudinally along the transistor die; and wherein the gate pad comprises a dimension longitudinally along the transistor die greater than a dimension extending laterally across the transistor die (Jeon, in a different embodiment shown in Fig. 13E, teaches a semiconductor device having drain pad 190, gate pad 194, drain pad 190 has a dimension extending laterally across the transistor die greater than a dimension extending longitudinally along the transistor die, while gate pad 194 has a dimension extending longitudinally along the transistor die greater than a dimension extending laterally across the transistor die. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the relative pad-dimension arrangement shown in the Figs. 13E embodiment of Jeon with the transistor-die layout taught in Fig. 8A in the same reference, in order to place the drain-side pad structure broadly across the output side of the die while placing the gate-side pad structure in a narrower orientation over the active area for routing and interconnection to the gate structure. Jeon itself teaches these as alternative layouts for the same class of multi-finger GaN transistor devices, so adopting the pad-shape arrangement of one disclosed embodiment in the die layout of another would have been a predictable layout optimization within the teachings of the same reference).
Re: Claim 4, Jeon discloses all the limitations of claim 1 on which this claim depends.
Jeon further discloses,
wherein a longer dimension of the gate pad extends longitudinally along the transistor die; and wherein a longer dimension of the at least one drain pad extends laterally across the transistor die (Jeon, in a different embodiment shown in Fig. 13E, teaches a semiconductor device having drain pad 190, gate pad 194; gate pad 194 has a longer dimension longitudinally along the transistor die, while drain pad 190 has a longer dimension extending laterally across the transistor die. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the relative pad-dimension arrangement shown in the Figs. 13E embodiment of Jeon with the transistor-die layout taught in Fig. 8A in the same reference, in order to place the drain-side pad structure broadly across the output side of the die while placing the gate-side pad structure in a narrower orientation over the active area for routing and interconnection to the gate structure. Jeon itself teaches these as alternative layouts for the same class of multi-finger GaN transistor devices, so adopting the pad-shape arrangement of one disclosed embodiment in the die layout of another would have been a predictable layout optimization within the teachings of the same reference).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20180026123 A1) in view of Shilmkar (US 20220115297 A1).
Re: Claim 15, Jeon discloses all the limitations of claim 1 on which this claim depends.
Jeon is silent regarding,
wherein the transistor die is configured as a flip chip.
However, Shilmkar teaches wherein the transistor die is configured as a flip chip (Shilmkar teaches, in ¶ [0017], teaches power die having a FET, a frontside input/output interface with gate, drain and source contact pads, and electrically conductive connection elements on those pads, where the conductive connection elements couple the power die in an inverted orientation with the pads facing the module substrate. Thus, Shilmkar teaches a transistor die configured as a flip chip).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to configure the transistor die of Jeon as a flip chip as taught by Shilmkar in order to provide a frontside pad arrangement suitable for inverted mounting to a substrate.
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20180026123 A1) in view of Kabir (US 20230260935 A1).
Re: Claim 17, Jeon discloses all the limitations of claim 1 on which this claim depends.
Jeon is silent regarding,
further comprising a second harmonic control capacitor arranged on the transistor die, wherein the second harmonic control capacitor comprises a second harmonic circuit connection; and wherein the second harmonic circuit connection connects the second harmonic control capacitor and/or the source fingers to a device.
However, Kabir teaches
further comprising a second harmonic control capacitor arranged on the transistor die, wherein the second harmonic control capacitor comprises a second harmonic circuit connection; and wherein the second harmonic circuit connection connects the second harmonic control capacitor and/or the source fingers to a device (Kabir, in Fig. 2A and ¶ [0041], teaches on-die harmonic termination circuit including capacitor 260 and inductor coil 256, where capacitor 260 makes up the capacitance of the harmonic terminal circuit and the circuit is configured to shunt signal energy at a harmonic frequency, including a second harmonic example. Kabir further teaches that the capacitor 260 is formed within build-up structure 290, that top plate 261 is connected to terminal 257 via conductive trace 275 and conductive via 272, and that bottom plate 262 is connected through conductive via 273, source bus 244 and TSV 246. Thus, capacitors 260 correspond to the claimed second harmonic control capacitor arranged on the transistor die, and the conductive path through trace 275 / vias 272, 273 / source bus 244 / TSV 246 correspond to the claimed second harmonic circuit connection that connects the capacitor to a device).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further provide the transistor die layout of Jeon with on-die second harmonic control capacitor and corresponding circuit connection as taught by Kabir, in order to control second-harmonic impedance, provide a low-impedance path for second harmonic energy, and achieving relatively high efficiency for broadband applications.
Re: Claim 18, Jeon and Kabir disclose all the limitations of claim 17 on which this claim depends.
Kabir further teaches
wherein the second harmonic circuit connection comprises a pillar (Kabir teaches, in Fig. 2A and ¶ [0039], capacitor 260 in a harmonic termination circuit, with top plate 261 connected to terminal 257 of inductor coil 256 via conductive trace 275 and conductive via 272, and bottom plate 262 connected to a ground node via conductive via 273, source bus 244, and source TSV 246. Accordingly, conductive via 272, conductive via 273, and TSV 246 are vertically extending conductive interconnect structures and thus the second harmonic circuit connection comprises a pillar).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the second harmonic circuit of the on-die harmonic-control capacitor using a vertically extending interconnect structure such as conductive via/TSV pillar, as taught by Kabir in the die-layout of Jeon, in order to provide compact die-level routing to the harmonic-termination circuit and a low-impedance vertical connection to the source/ground-side structure.
Re: Claim 19, Jeon and Kabir disclose all the limitations of claim 17 on which this claim depends.
Kabir further teaches
wherein the second harmonic control capacitor is implemented with a metal insulator metal (MIM) configuration arranged on the transistor die (Kabir teaches, in ¶ [0038], capacitor 260 including top plate 261 and bottom plate 262, with top plate 261 formed in patterned conductive layer 295, bottom plate 262 formed in a patterned conductive layer 292, and the two plates separated by dielectric layers of build-up structure 290. Accordingly, that is a metal insulator metal (MIM) configuration arranged on the transistor die).
Claim(s) 20-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20180026123 A1) in view of Blednov (US 20120146723 A1).
Re: Claim 20, Jeon discloses all the limitations of claim 1 on which this claim depends.
Jeon is silent regarding,
further comprising an output capacitor arranged on the transistor die and configured as an output series capacitor.
However, Blednov teaches
further comprising an output capacitor arranged on the transistor die and configured as an output series capacitor (Blednov teaches, in ¶ [0047], amplifier 600 having a series capacitor Cser 621 added to the output of active device 601, teaches that series capacitor 621 can be provided on active device 601 as part of the output, and further teaches that the series capacitance 621 is connected between drain bar 613 and separate output bar 602 of active die 601. According capacitor 621 corresponds to an output capacitor arranged on the transistor die and configured as an output series capacitor).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further provide the transistor die layout of Jeon with an on-die series capacitor as taught by Blednov, in order to compensate for the output-lead inductance and contribute to the required impedance transformation on the PCB (Blednov, ¶ [0047]).
Re: Claim 21, Jeon and Blednov disclose all the limitations of claim 20 on which this claim depends.
Blednov further teaches
wherein the output capacitor connects to an implementation of the at least one drain pad (Blednov teaches, ¶ [0048], the series capacitor 621 is provided on the active device 601 as part of the output, and that the series capacitance 621 is connected between the drain bar 613 and a separate output bar 602 of the active die 601. Accordingly, drain bar 613 is an implementation of the at least one drain pad, and thus the output capacitor connects to an implementation of the at least one drain pad).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to connect the on-die output series capacitor of the transistor die to a drain-pad implementation as taught by Blednov in order to place the series output capacitor directly in the drain-side output path for impedance transformation (Blednov, ¶ [0047]).
Re: Claim 22, Jeon and Blednov disclose all the limitations of claim 20 on which this claim depends.
Blednov further teaches
wherein the output capacitor comprises a capacitor connection to a device (Blednov teaches, in ¶¶ [0047] - [0048], that series capacitance 621 is provided on active device 601 as part of the output, and that the series capacitance 621 is connected between drain bar 613 and a separate output bar 602 of the active die 601. Thus, series capacitance 621 teaches the claimed output capacitor, and separate output bar 602 teaches the claimed capacitor connection to a device).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide the transistor die of Jeon with the on-die output series capacitor and output-side capacitor connection taught by Blednov in order to compensate for inductance of the output RF lead and contribute to the required output impedance transformation.
Claims 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20180026123 A1) in view of Blednov (US 20120146723 A1) further in view of Bacon (US 20110095824 A1).
Re: Claim 23, Jeon and Blednov disclose all the limitations of claim 22 on which this claim depends.
Jeon and Blednov are silent regarding
wherein the capacitor connection comprises a pillar.
However, Bacon teaches wherein the capacitor connection comprises a pillar (Bacon, teaches, in ¶ [0008] an RF power amplifier integrated circuit having capacitors on the integrated circuit, contact pads disposed on top of the capacitors (Bacon, ¶ [0014]), and that such contact pads may be contacted by flip-chip mounting, including Cu pillars).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the output-capacitor connection of Blednov with the flip-chip pillar connection taught by Bacon in order to provide a compact chip-level electrical connection to a capacitor structure in an RF power amplifier integrated circuit.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20180026123 A1) in view of Blednov (US 20120146723 A1) further in view of Wang (US 20020097094 A1).
Re: Claim 24, Jeon and Blednov disclose all the limitations of claim 20 on which this claim depends.
Jeon and Blednov are silent regarding
wherein the output capacitor is implemented with a metal insulator metal (MIM) configuration arranged on the transistor die.
However, Wang teaches wherein the output capacitor is implemented with a metal insulator metal (MIM) configuration arranged on the transistor die (Wang teaches, in ¶ [0013], that output matching circuit capacitors on semiconductor body 20 comprise metal-insulator-metal (MIM) capacitors, and teaches MIM capacitors 24, 26 mounted on the major surface of semiconductor body 20, including a series element implementation).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the on-die output series capacitor of Blednov as a MIM capacitor as taught by Wang in order to provide an integrated on-chip output matching capacitor with known MIM benefits for RF output networks.
Claim(s) 25, 29, 34-35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20180026123 A1) in view of Schultz (US 10250197 B1).
Re: Claim 25, Jeon discloses all the limitations of claim 1 on which this claim depends.
Jeon is are silent regarding
further comprising an integrated passive device (IPD).
However, Schultz teaches further comprising an integrated passive device (IPD) (Schultz teaches, in column 22 lines 56-64, device 600 including GaN final stage IC die 680 and an output integrated passive device (IPD) 698 physically connected to substrate 606. Schultz further teaches, in column 24 lines 45-57, that IPD 698 may include capacitors, inductors, and/or resistors forming portions of an output impedance matching circuit. Thus, Schultz teaches the claimed device comprising the transistor die and further comprising an integrated passive device (IPD)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the transistor die of Jeon in a device further including an IPD, as taught by Schultz, in order to provide integrated passive functionality for output impedance matching on the same device/package.
Re: Claim 29, Jeon and Schultz disclose all the limitations of claim 25 on which this claim depends.
Schultz further teaches
further comprising a shunt L circuit implemented at least in part on the device and connected to the at least one drain pad by a drain pad connection (Schultz teaches device 600 including a GaN final stage IC die 680 and an IPD 698, and further teaches, in column 24 lines 65-column 25 lines 7, that wirebonds 699 between the output terminal 692 of the die and the IPD 698 may function as a shunt inductive component of the output matching circuit. Schultz also teaches that passive components within IPD 698 are electrically coupled to wirebonds 699 and may function as additional shunt components in the shunt circuit. Thus, Schultz teaches a shunt L circuit implemented at least in part on the device and connected to the at least one drain pad by a drain pad connection).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide the device including the transistor die of Jeon with the shunt inductive output-matching arrangement taught by Schultz in order to implement part of the output matching circuit on the device/IPD while connecting that shunt inductive path to the drain-side output node of the transistor die.
Re: Claim 34, Jeon and Schultz disclose all the limitations of claim 25 on which this claim depends.
Jeon and Schultz further teach
further comprising: an input configured to form an RF input for the device and the input being connected to the gate pad; and an output configured to form an RF output for the device and the output being connected to the at least one drain pad; and wherein the output is configured on an axis at least semi-orthogonally to an axis of the input (Schultz teaches, in column 33 lines 56-65, a first die having a first RF signal input terminal and a first RF signal output terminal, where the control terminal of the first transistor is electrically couple to the first RF signal input terminal and the current-carrying terminal electrically coupled to the first RF signal output terminal. Thus, Schultz teaches an input configured to form an RF input for the device and an output configured to form an RF output for the device, with the input connected to the transistor control/gate side and the output connected to the transistor current-carrying/drain side. Under the broadest reasonable interpretation, because the RF input is associated with the gate pad and the RF output is associated with the drain pad, the output axis is treated as following the drain-pad axis and the input axis is treated as following the gate-pad axis; therefore, as shown in claim 1 rejection with Jeon to the extent the drain-pad axis is at least semi-orthogonal to the gate-pad axis, the output is configured on an axis at least semi-orthogonally to an axis of the input.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide the transistor-die layout of Jeon with the RF input/output terminal arrangement taught by Schultz in order to implement the disclosed gate-side structure as an RF input and the disclosed drain-side structure as an RF output in an RF device.
Re: Claim 35, Jeon and Schultz disclose all the limitations of claim 25 on which this claim depends.
Regarding the limitation “further comprising a capacitor configured as part of FO high pass capacitor circuit connected to the source fingers”, Schultz teaches an IPD 698 including capacitors configured as part of output impedance matching circuit, wherein the output impedance matching circuit may include a high-pass circuit. Schultz further teaches that the shunt circuit may include a shunt capacitor having a first terminal electrically coupled to the output terminal 692 of the GaN final-stage IC die 680 and a second terminal electrically coupled to a ground node.
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the Jeon device to include the capacitor/high-pass matching circuit taught by Schultz, with the capacitor connected to the source fingers/source pad of Jeon, since the source fingers are electrically coupled to the source pad and serve as the transistor source/reference node, and Schultz teaches using a capacitor-containing high-pass/output matching circuit to improve RF impedance matching and reduce the amount of external PCB matching circuitry required.
Claim(s) 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20180026123 A1) in view of Schultz (US 10250197 B1) and further in view of Blednov (US 20120146723 A1).
Re: Claim 33, Jeon and Schultz disclose all the limitations of claim 25 on which this claim depends.
Jeon and Schultz are silent regarding
further comprising a wide band application circuit that comprises an output capacitor arranged on the transistor die.
However, Blednov teaches further comprising a wide band application circuit that comprises an output capacitor arranged on the transistor die (Blednov teaches a radiofrequency amplifier having an output impedance matching network comprising a series high-pass network provided at least partly on the active die, and expressly teaches that the series capacitor 621 can be provided on the active device 601 as part of the output. Blednov further states that the amplifier can have improved bandwidth and improved broad band VBW. Thus, Blednov teaches a wide band applicantion circuit that comprises an output capacitor arranged on the transistor die).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further provide the device of Jeon and Schultz with the wideband output-matching arrangement taught by Blednov in order to implement an on-die output capacitor within a wideband RF application circuit and thereby improve bandwidth while maintaining a compact die/package output network. Blednov expressly teaches on-die series capacitor 621 at the active-die output and ties that arrangement to improved bandwidth and improved broad band VBM.
Claim(s) 37-39 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20180026123 A1) in view of Schultz (US 10250197 B1) and further in view of Moronval (US 20150145601 A1).
Re: Claim 37, Jeon and Schultz disclose all the limitations of claim 25 on which this claim depends.
Jeon and Schultz are silent regarding
wherein the transistor die comprises two separate transistor devices combined.
However, Moronval teaches
wherein the transistor die comprises two separate transistor devices combined (Moronval teaches, in ¶¶ [0005] - [0006] an integrated Doherty amplifier comprising a main amplifier, at least a first and a second peak amplifier, each of the amplifiers comprising a gate for receiving the input signal, a source and a drain, and expressly teaches, in ¶ [0031], that the main amplifier and peak amplifier may be provided on a single die).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the transistor die of the device of Jeon and Schultz so that the die includes two separate transistor devices on the same die, as taught by Moronval, in order to integrate multiple amplifier/transistor functions on one die and reduce die-to-die interconnections while preserving compact RF device layout.
Re: Claim 38, Jeon and Schultz disclose all the limitations of claim 25 on which this claim depends.
Jeon and Schultz are silent regarding
wherein the transistor die comprises two separate discrete transistor devices.
However, Moronval teaches
wherein the transistor die comprises two separate discrete transistor devices (Moronval teaches, in ¶¶ [0005] - [0006] an integrated Doherty amplifier comprising a main amplifier, at least a first and a second peak amplifier, each of the amplifiers comprising a gate for receiving the input signal, a source and a drain, and expressly teaches, in ¶ [0031], that the main amplifier and peak amplifier may be provided on a transistor die. Hence, Moronval teaches the transistor die comprises two separate discrete transistor devices).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the transistor die of the device of Jeon and Schultz so that the die includes two separate transistor devices on the same transistor die, as taught by Moronval, in order to integrate multiple amplifier/transistor functions on one die and reduce die-to-die interconnections while preserving compact RF device layout.
Re: Claim 39, Jeon and Schultz disclose all the limitations of claim 25 on which this claim depends.
Jeon and Schultz are silent regarding
further comprising a second transistor, wherein the transistor and the second transistor comprise two separate discrete devices configured in a Doherty implementation.
However, Moronval teaches
further comprising a second transistor, wherein the transistor and the second transistor comprise two separate discrete devices configured in a Doherty implementation (Moronval teaches, in ¶¶ [0005] - [0006] an integrated Doherty amplifier comprising a main amplifier, at least a first and a second peak amplifier, each of the amplifiers comprising a gate for receiving the input signal, a source and a drain, and expressly teaches, in ¶ [0031], that the main amplifier and peak amplifier may be provided on a transistor die. Hence, Moronval teaches the transistor die comprises two separate discrete devices configured in a Doherty implementation).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the transistor die of the device of Jeon and Schultz so that the die includes two separate discrete devices on the same transistor die configured in a Doherty implementation, as taught by Moronval, in order to integrate multiple amplifier/transistor functions on one die and reduce die-to-die interconnections while preserving compact RF device layout.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
Radulescu (US 20230075505 A1) and Trang (US 20200343352 A1) disclose RF devices with interior fingers.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIPANA ADHIKARI DAWADI whose telephone number is (571)272-4149. The examiner can normally be reached Monday-Friday 11:30am-7:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BIPANA ADHIKARI DAWADI/ Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
Prosecution Insights