DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species B, Figure 13 (Claims 1-20) in the reply filed on 4/8/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 9-15 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Sato (20160272500), hereinafter Sato.
Regarding claim 1, Sato (20160272500) (refer to Figure 1A-Figure 4C, also see para 30) teaches an interconnect structure (described as “wiring structures” in para 30, i.e. a structure to serve as interconnect), comprising
a conductive feature (comprising 26, 33 – described as "graphene plug 26" in para 47 and "graphene wiring layer 33" in para 61) embedded in a dielectric feature (25, described as “interlayer insulating film 25” which may be “silicon oxide” – see para 47; also 32 described in para 61), and
having a horizontal portion (26 or 33) including graphene layers (para 47 describes 26 is formed from "multilayer graphene 24" and para 61 describes 33 is made from “multilayer graphene 31”) stacked on each other; and
a metal-including intercalation material (such as “at least one of” a list of materials that includes FeCl3 or Cs or Li described for “intercalation” in para 48) interposed among the graphene layers (para 49).
Regarding claim 2, Sato (refer to Figure 1A-Figure 4C) teaches the interconnect structure according to claim 1, wherein the metal-including intercalation material includes a first atom dopant having one of a group 1 metal, a group 2 metal, a group 3 metal, a lanthanide series metal, an actinide series metal, and combinations thereof (at least Li is disclosed in para 48, which is a group 1 metal).
Regarding claim 3, Sato (refer to Figure 1A-Figure 4C) teaches the interconnect structure according to claim 2, wherein the first atom dopant includes one of lithium, caesium, rubidium, calcium, sodium, strontium, barium, potassium, and combinations thereof (at least “Li” is disclosed in para 48; i.e. lithium).
Regarding claim 9, Sato (refer to Figure 1A-Figure 4C) teaches the interconnect structure according to claim 1, wherein the metal-including intercalation material includes a metal halide (see para 48 for list of intercalation materials that includes FeCl3).
Regarding claim 10, Sato (refer to Figure 1A-Figure 4C) teaches the interconnect structure according to claim 9, wherein the metal halide includes one of arsenic pentafluoride, antimony pentafluoride, iron (III) chloride, and combinations thereof (see para 48 for list of intercalation materials that includes FeCl3; i.e. at least the claimed “iron (III) chloride”)
Regarding claim 11, Sato (refer to modification example 1 of Figure 7, see para 92) teaches an interconnect structure (described as “wiring structures” in para 30, i.e. a structure to serve as interconnect; also see para 92), comprising
a conductive feature (comprising 42a, 42b, 33 – described as "graphene wiring layer 33" in para 61, and “W Plug 42” in para 94) embedded in a dielectric feature (25, described as “interlayer insulating film 25” which may be “silicon oxide” – see para 47; also 32 described in para 61), and
having a first horizontal portion (33) extending in a horizontal direction (left-right direction in orientation of Figure 7) to terminate at two edge surfaces (top and bottom edge of 33 in orientation of Figure 7), and including graphene layers stacked on each other (para 61 describes 33 is made from “multilayer graphene 31”), and
an intercalation material (such as “at least one of” a list of materials that includes FeCl3 or Cs or Li described for “intercalation” in para 48) interposed among the graphene layers, the intercalation material including a first atom dopant including one of a group 1 metal, a group 2 metal, a group 3 metal, a lanthanide series metal, an actinide series metal, and combinations thereof (at least Li is disclosed in para 48, which is a group 1 metal), and
a first vertical portion (42b of Figure 7, see para 94) extending in a vertical direction (up-down direction in orientation of Figure 7) and being in contact with one of the two edge surfaces (i.e. lower horizontal edge of 33) of the first horizontal portion (33), the first vertical portion (42b of Figure 7, see para 94) being made of a first electrically conductive metal material (such as “tungsten” described in para 94).
Regarding claim 12, Sato (refer to modification example 1 of Figure 7, see para 92) teaches the interconnect structure according to claim 11, wherein the first electrically conductive metal material includes ruthenium, copper, tungsten, titanium, aluminum, cobalt, molybdenum, iridium, rhodium, or combinations thereof (“tungsten” described as material of 422b in para 94)
Regarding claim 13, Sato (refer to modification example 1 of Figure 7, see para 92) teaches the interconnect structure according to claim 11, wherein the conductive feature further includes a second vertical portion (43b, see Figure 7 and para 95) extending away from the first vertical portion in the vertical direction (see Figure 7).
Regarding claim 14, Sato (refer to modification example 1 of Figure 7, see para 92) teaches the interconnect structure according to claim 11, wherein: the first horizontal portion (33) has an upper surface and a lower surface opposite to the upper surface in the vertical direction (i.e. up-down direction in orientation of Figure 7); and the conductive feature further includes a second horizontal portion (43b, which may be Cu – see para 95) which is in contact with one of the upper surface and the lower surface (i.e. in contact with upper surface) of the first horizontal portion (33), and which is made of a second electrically conductive metal material (para 95 discloses 43b may be Cu – see para 95), the second horizontal portion extending in the horizontal direction (43b extends both in horiztonal and vertical direction) and being in contact (i.e. in electrical contact through 33) with the first vertical portion (42b).
Regarding claim 15, Sato (refer to modification example 1 of Figure 7, see para 92) teaches the interconnect structure according to claim 14, wherein the second electrically conductive metal material includes ruthenium, copper, tungsten, titanium, aluminum, cobalt, molybdenum, iridium, rhodium, or combinations thereof (para 95 discloses 43b may be Cu – see para 95).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 4 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Sato in view of Feygenson (US 9870925), hereinafter Feygenson.
Regarding claim 4, Sato (refer to Figure 1A-Figure 4C) teaches the interconnect structure according to claim 2, but does not teach that between two adjacent ones of the graphene layers, first atoms of the first atom dopant are arranged “as a single atomic layer”. Feygenson (US 9870925) teaches that the use of a monolayer of dopant atoms (Col. 10, lines 8-17; also see Col. 12, lines 51-67) is known. It would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to modify Sato so that between two adjacent ones of the graphene layers, first atoms of the first atom dopant are arranged “as a single atomic layer”. The ordinary artisan would have been motivated to modify Sato for at least the purpose of creating the graphene feature with minimal thickness, so as to miniaturize the device without sacrificing electrical conductivity.
Regarding claim 16, Sato (20160272500) (refer to Figure 1A-Figure 4C, also see para 30) teaches an interconnect structure (described as “wiring structures” in para 30, i.e. a structure to serve as interconnect), comprising a conductive feature (comprising 26, 33 – described as "graphene plug 26" in para 47 and "graphene wiring layer 33" in para 61) embedded in a dielectric feature (25, described as “interlayer insulating film 25” which may be “silicon oxide” – see para 47; also 32 described in para 61), and
having a first horizontal portion (26 or 33) including graphene layers (para 47 describes 26 is formed from "multilayer graphene 24" and para 61 describes 33 is made from “multilayer graphene 31”) stacked on each other, and
an intercalation material (such as “at least one of” a list of materials that includes FeCl3 or Cs or Li described for “intercalation” in para 48) interposed among the graphene layers, the intercalation material including a first atom dopant including one of a group 1 metal, a group 2 metal, a group 3 metal, a lanthanide series metal, an actinide series metal, and combinations thereof (at least Li is disclosed in para 48, which is a group 1 metal), but does not teach first atoms of the first atom dopant between two adjacent ones of the graphene layers being arranged “as a single atomic layer”.
Feygenson (US 9870925) teaches that the use of a monolayer of dopant atoms (Col. 10, lines 8-17; also see Col. 12, lines 51-67) is known. It would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to modify Sato so that first atoms of the first atom dopant between two adjacent ones of the graphene layers being arranged “as a single atomic layer”. The ordinary artisan would have been motivated to modify Sato for at least the purpose of creating the graphene feature with minimal thickness, so as to miniaturize the device without sacrificing electrical conductivity.
Allowable Subject Matter
Claims 5-8 and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Claim 5 is allowable because the prior art of record does not teach or suggest, singularly or in combination, at least the limitations requiring “two adjacent ones of the first atoms between two adjacent ones of the graphene layers are spaced apart by an in-between distance which is not greater than a bulk bond length of atoms that are present in a bulk and that are of the same element as the first atoms”.
Claims 6-8 are allowable because the prior art of record does not teach or suggest, singularly or in combination, at least the limitations of base claim 6 that requires “the metal-including intercalation material further includes a second atom dopant, a binding energy between the second atom dopant and the graphene layers being greater than a binding energy between the first atom dopant and the graphene layers”.
Claims 17-20 are allowable because the prior art of record does not teach or suggest, singularly or in combination, at least the limitations of base claim 17 that requires “a binding energy between the second atom dopant and the graphene layers being greater than a binding energy between the first atom dopant and the graphene layers, between two adjacent ones of the graphene layers, the first atoms of the first atom dopant” in conjunction with “second atoms of the second atom dopant are arranged as a single atomic layer”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AJAY ARORA whose telephone number is (571)272-8347. The examiner can normally be reached 9 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Drew Richards can be reached at 5712721736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AJAY ARORA/Primary Examiner, Art Unit 2892