Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on January 9, 2024 and January 27, 2026 are being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
In para [0004] and [0042] HGGA should read HGAA.
Appropriate correction is required.
Claim Objections
Claims 12-20 are objected to because of the following informalities:
In claim 12, “HGGA” should read “horizontal gate all around (HGAA)”
In claim 13, “HGGA” should read “horizontal gate all around (HGAA)”
In claim 14, “forming a superlattice on first substrate” should read “forming a superlattice on the first substrate”
In claim 15, “that different thickness” should read “the different thicknesses”
In claim 15, the second semicolon at the end of the second section should be deleted
In claim 20, “/” should be replaced by “.”
Appropriate correction is required.
Dependent claims 15-20 are objected to at least on the same basis as claim 15 upon which they depend.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites the limitation "the substrate" in line 3. There is insufficient antecedent basis for this limitation in the claim. It is unclear if “the substrate” refers to “the first substrate” or “the second substrate.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Examiner’s Note: The Examiner considers the limitation “wherein the amount of first material removed from the first sub-layer of the first material is greater than the amount of material removed from the second sub-layer of the first material;” to be inherent to the method of removing the first material from the sublayer based on the Applicant’s recitation of “Here, the etching to trim the first to third wire preforms 52 - 56 is isotropic, or primarily so, such that an nearly equal thickness of silicon will be removed uniformly over the exposed outer surfaces of an individual first to third wire preforms 52 - 56, although different thicknesses will inherently be etched away on different ones of the wire preforms 52, 54, 56 at their different distances from the upper surface of the substrate 2.” in para. [0064] of the specification. The Examiner therefore takes the position that trimming the nanowires of a gate all around transistor through a plasma etch process inherently results in different amounts of material being removed because the recitation of the method in the specification enables the claims.
Further, the Examiner considers the limitation “wherein the thickness of the capping layer formed on the first trimmed sub-layer of the first material of the second superlattice is greater than the thickness of the capping layer formed on the second trimmed sub- layer of the first material of the second superlattice” to be inherent to the method of depositing the capping material based on the Applicant’s recitation of “the thickness of the epitaxially grown silicon germanium capping layer 24 is inherently thinner over the trimmed wire preform 56c' closest to the substrate 2 (and thus deeper in the trench 11), as compared to that formed on the first post trim wire preform 52' furthest from the substrate 2.” in para. [0061]. The Examiner therefore takes the position that depositing an SiGe capping layer with an epitaxial deposition process inherently results in capping layers with different thicknesses because the recitation of the method in the specification enables the claims.
The Examiner further notes that several claims require thicknesses of different parts to be “equal.” The instant invention solves a problem relating to the inherent nonuniformity of processes described above which causes products designed to have uniform channels or gates to have some nonuniformity. Because the Applicant has not defined in the specification or claims the degree of precision required for two thicknesses to be considered “equal” the Examiner will consider any method in which the claimed thicknesses are designed to be equal to meet the limitation even if the prior art does not describe how the inherent nonuniformity is mitigated.
Claims 1-6, 14, 16, 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Colombeau (US 2020/0152493 A1) in view of Tanaka (US 2004/0040930 A1).
With respect to claim 1, Colombeau teaches:
A method of forming a semiconductor device, comprising:
forming a first superlattice (alternating layers 6, 8) on a first substrate (substrate 2) (para. 55 “A superlattice is formed on the substrate 2. The superlattice includes alternating layers 6, 8 of different materials.”),
the first superlattice comprising alternating sub-layers of a first material (8) comprising a semiconductor and sub-layers of a second material (6),
wherein the thicknesses of the first material sub-layers (8) are a first thicknesses and the thicknesses of the second material sub-layers are a second thickness (6),
wherein at least a first sub layer of the first material (second from bottom 8) and a second sub layer of the first material (bottommost 8) are formed in the first superlattice,
the second sublayer of the first material interposed between the first sublayer of the first material and the substrate;
removing the sub-layers of the second material (6) from the first superlattice (see Fig. 10A and 10B);
etching the first and second sub-layers of the first material of the first superlattice to remove a portion of the first material thereof and form a first trimmed sub-layer of the first material and a second trimmed sub-layer of the first material (See Fig. 11A and 11B, trimming process from 8 to 8’),
wherein the amount of first material removed from the first sub-layer of the first material is greater than the amount of material removed from the second sub-layer of the first material(the trimming process is described by Colombeau is para. 69 and uses a mixture of NF3 and He gas, similar to the process described in the specification of the instant application. The Examiner determines that this limitation is inherent to the etching process as described in the Examiner’s note above);
and depositing a capping layer over the first trimmed sub-layer of the first material of the first superlattice, over the second trimmed sub-layer of the first material of the first superlattice, and on an exposed surface of the substrate (para. 70 “The epitaxial growth process forms cladding layers 24 on the trimmed layers 8′ and exposed surfaces of the substrate 2. The cladding layers 24 are on the exposed surfaces of the trimmed layers 8′ and substrate 2”);
Colombeau fails to teach:
measuring the distance between the capping layer on the first sub-layer and the capping layer on the second sublayer, and the distance between the capping layer on the second sub-layer and the capping layer on the substrate,
and determining a first difference between those distances;
forming a second superlattice on a second substrate,
the second superlattice comprising alternating sub-layers of the first material comprising a semiconductor and sub-layers of the second material,
wherein the thicknesses of the first material sub-layers are a first thicknesses and the thicknesses of the second material sub- layers are a second thickness,
wherein at least a first sub layer of the first material and a second sub layer of the first material are formed in the second superlattice,
the second sublayer of the first material interposed between the first sublayer of the first material and the second substrate; removing the sub-layers of the second material from the second superlattice and the second substrate;
etching the first and second sub-layers of the first material of the second superlattice to remove a portion of the first material thereof and form a first trimmed sub-layer of the first material and a second trimmed sub-layer of the first material,
wherein the process conditions used to remove the portions of the first sub-layer of the first material and of the second sub-layer of the first material are different than those used to remove portions of the first sub-layer of the first material and the second sublayer of the first material of the first superlattice;
and depositing a capping layer over the first trimmed sub-layer of the first material of the second superlattice and over the second trimmed sub-layer of the first material of the second superlattice and on an exposed surface of the substrate;
wherein, the difference between the distance between the capping layer on the first sub-layer of the first material and the capping layer on the second sublayer of the first material of the second superlattice and the distance between the capping layer on the second sub-layer of the first material of the second superlattice and the capping layer on the second substrate is less than the first difference.
Tanaka teaches that it is known to iteratively determine etch process parameters based on target etch characteristics by using three-dimensional shape data of a pattern from an SEM image to adjust etching-process conditions for a next wafer. Therefore, applying the teachings of Tanaka to repeat the process of Colombeau with different conditions teaches:
measuring the distance between the capping layer on the first sub-layer and the capping layer on the second sublayer, and the distance between the capping layer on the second sub-layer and the capping layer on the substrate (para. 51 “Next, by use of the length measuring SEM 200, an electron beam image of the circuit pattern after etching is picked up (step 1005), thereafter the shape of the pattern is evaluated by use of the electron beam image (step 1006), and the results thus obtained are displayed on a screen (step 1007). Based on the evaluation results obtained, the operator evaluates the acceptability of the pattern shape, then determines the step or steps of which the process conditions are to be modified and sets new conditions (steps 1008, 1009).”),
and determining a first difference between those distances;
forming a second superlattice on a second substrate (“treatment of the next wafer of step 1008),
the second superlattice comprising alternating sub-layers of the first material comprising a semiconductor and sub-layers of the second material,
wherein the thicknesses of the first material sub-layers are a first thicknesses and the thicknesses of the second material sub- layers are a second thickness,
wherein at least a first sub layer of the first material and a second sub layer of the first material are formed in the second superlattice,
the second sublayer of the first material interposed between the first sublayer of the first material and the second substrate; removing the sub-layers of the second material from the second superlattice and the second substrate;
etching the first and second sub-layers of the first material of the second superlattice to remove a portion of the first material thereof and form a first trimmed sub-layer of the first material and a second trimmed sub-layer of the first material,
wherein the process conditions used to remove the portions of the first sub-layer of the first material and of the second sub-layer of the first material are different than those used to remove portions of the first sub-layer of the first material and the second sublayer of the first material of the first superlattice (“modification of etching recipe of step 1008);
and depositing a capping layer over the first trimmed sub-layer of the first material of the second superlattice and over the second trimmed sub-layer of the first material of the second superlattice and on an exposed surface of the substrate;
wherein, the difference between the distance between the capping layer on the first sub-layer of the first material and the capping layer on the second sublayer of the first material of the second superlattice and the distance between the capping layer on the second sub-layer of the first material of the second superlattice and the capping layer on the second substrate is less than the first difference.
It would have been obvious to one of ordinary skill in the art at the time of the invention to adapt the method of iteratively adjusting etching recipes based on measurements of an etched device to the gate all around structure of Colombeau as taught by Tanaka because the market place reflects the reality that iteratively determining the etching conditions to obtain a desired product is commonplace and using results from a first etching process to make a product under different etching conditions as claimed would result from the application of the prior knowledge or known method as demonstrated by Tanaka in a predictable manner. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 2-4, although Tanaka does not specify which etching conditions are adjusted, Colombeau teaches in para. 66 that process conditions for the etching include ratio of NF3:He, flow rate, pressure, power, and frequency. The Examiner also takes official notice that is well known in the art that the amount of time a semiconductor is exposed to etching gas affects the amount etched away. It would be obvious to a person of ordinary skill in the art to use include any of these properties in the etching conditions that are adjusted in the method of Colombeau modified by Tanaka. Therefore:
With respect to claim 2, Colombeau/Tanaka teaches:
wherein the process pressure (para. 66 “A pressure in the chamber 122 can be maintained in a range from 0.25 Torr to about 2 Torr.”) during the etching of the first sub-layer of the first material and second sublayer of the first material on the second superlattice is lower than the process pressure during the etching of the first sub-layer of the first material and second sublayer of the first material on the first superlattice.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adjust the pressure, gas concentration ratio, and process time to meet the limitations above with routine experiment and optimization. The ordinary artisan would be motivated to do so because it is known in the art that the process conditions claimed can be used to tune the etch rate in order to obtain a desired etched profile. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
With respect to claim 3, Colombeau/Tanaka teaches:
wherein the relative concentration of the gases (para. 66 “The mixture of nitrogen trifluoride (NF.sub.3) and helium (He) can be in a ratio in a range from 1:350 (NF.sub.3:He) to 1:120 (NF.sub.3:He),”) during the etching of the first sub-layer of the first material and the second sublayer of the first material on the second superlattice is the same as the relative concentrations of the gases used to etch the first sub-layer of the first material and second sublayer of the first material on the first superlattice.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adjust the pressure, gas concentration ratio, and process time to meet the limitations above with routine experiment and optimization. The ordinary artisan would be motivated to do so because it is known in the art that the process conditions claimed can be used to tune the etch rate in order to obtain a desired etched profile. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
With respect to claim 4, Colombeau/Tanaka further teaches:
wherein the process time during the etching of the first sub-layer of the first material and the second sublayer of the first material on the second superlattice is longer than the process time used to etch the first sub-layer of the first material and second sublayer of the first material on the first superlattice.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adjust the pressure, gas concentration ratio, and process time to meet the limitations above with routine experiment and optimization. The ordinary artisan would be motivated to do so because it is known in the art that the process conditions claimed can be used to tune the etch rate in order to obtain a desired etched profile. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
With respect to claim 5, Colombeau further teaches:
wherein the sum of the thicknesses of the capping layer (24) formed on the first trimmed sub-layer (second from bottom 8’) of the first material of the second superlattice and the thickness of the first trimmed sub-layer of the first material of the second superlattice is equal to the sum of the thicknesses of the capping layer formed on the second trimmed sub-layer of the first material of the second superlattice (lowermost 8’) and the thickness of the second trimmed sub-layer of the first material of the second superlattice. (Colombeau teaches that for all instances of 8 has a thickness in the range of 5 to 10 nm and that the trimming process removes 2 to 3 nm. Fig. 12B shows that the thicknesses are designed to be equal.)
In the event that Colombeau does not teach that the sums of the thicknesses are equal do to inherent limits of the process, which the Examiner does not concede, it would be obvious to adjust the parameters as taught by Tanaka to meet the above limitation for the purpose of improving the uniformity of the replacement gate structure, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
With respect to claim 6, Colombeau further teaches:
wherein the thickness of the capping layer formed on the first trimmed sub-layer of the first material of the second superlattice is greater than the thickness of the capping layer formed on the second trimmed sub- layer of the first material of the second superlattice (the process for growing the SiGe cladding layer is described in para. 71 of Colombeau and is similar to the process described in the specification of the instant application. The Examiner takes the position that this limitation is inherent to the deposition process, see Examiner’s note above.)
With respect to claim 14, Colombeau teaches:
A method of forming a multi-layer semiconductor device, comprising:
providing a first substrate (substrate 2);
forming a first superlattice (alternating layers 6, 8) on first substrate (substrate 2) (para. 55 “A superlattice is formed on the substrate 2. The superlattice includes alternating layers 6, 8 of different materials.”),
the superlattice comprising a plurality of alternating first layers composed of a first material (8) and second layers formed of a second material (6);
selectively removing the second layers of the superlattice (see Fig. 10A and 10B);
exposing the first layers of the superlattice to an etchant using first process conditions and removing a portion of the first material therefrom to form trimmed first layers therefrom, wherein the quantity of material removed from different ones of the first layers are different amounts (See Fig. 11A and 11B, trimming process from 8 to 8’);
forming a capping layer over the first layers in the superlattice stack (para. 70 “The epitaxial growth process forms cladding layers 24 on the trimmed layers 8′ and exposed surfaces of the substrate 2. The cladding layers 24 are on the exposed surfaces of the trimmed layers 8′ and substrate 2”);
Colombeau fails to teach:
measuring at least one of the distance between the capping layers formed on the different ones of the first layers, the thicknesses of the different ones of the capping layers formed on different ones of the trimmed first layers, and the different thicknesses of the combined thickness of different ones of the trimmed first layers and the capping layer formed thereover;
and based on the differences between at least one of the distance between the capping layers formed on the different ones of the first layers, the thicknesses of the different ones of the capping layers formed on different ones of the trimmed first layers, and the different thicknesses of the combined thickness of different ones of the trimmed first layers and the capping layer formed thereover,
calculating a new thickness of the trimmed first layers.
Tanaka teaches that it is known to iteratively determine etch process parameters based on target etch characteristics by using three-dimensional shape data of a pattern from an SEM image to adjust etching-process conditions for a next wafer. Therefore, applying the teachings of Tanaka to use an SEM to measure the characteristics of an etch profile and use the measurements to update process parameters renders obvious:
measuring at least one of the distance between the capping layers formed on the different ones of the first layers, the thicknesses of the different ones of the capping layers formed on different ones of the trimmed first layers, and the different thicknesses of the combined thickness of different ones of the trimmed first layers and the capping layer formed thereover (para. 51 “Next, by use of the length measuring SEM 200, an electron beam image of the circuit pattern after etching is picked up (step 1005), thereafter the shape of the pattern is evaluated by use of the electron beam image (step 1006), and the results thus obtained are displayed on a screen (step 1007).”);
and based on the differences between at least one of the distance between the capping layers formed on the different ones of the first layers, the thicknesses of the different ones of the capping layers formed on different ones of the trimmed first layers, and the different thicknesses of the combined thickness of different ones of the trimmed first layers and the capping layer formed thereover, calculating a new thickness of the trimmed first layers (“Based on the evaluation results obtained, the operator evaluates the acceptability of the pattern shape, then determines the step or steps of which the process conditions are to be modified and sets new conditions (steps 1008, 1009).”).
It would have been obvious to one of ordinary skill in the art at the time of the invention to adapt the method of iteratively adjusting etching recipes based on measurements of an etched device to the gate all around structure of Colombeau as taught by Tanaka because the market place reflects the reality that iteratively determining the etching conditions to obtain a desired product is commonplace and using results from a first etching process to make a product under different etching conditions as claimed would result from the application of the prior knowledge or known method as demonstrated by Tanaka in a predictable manner. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 16, applying the teachings of Tanaka to Colombeau to repeat the manufacturing process using updated etching parameters teaches:
further comprising providing a second substrate;
forming a superlattice the second substrate,
the superlattice comprising a plurality of alternating first layers composed of a first material and second layers formed of a second material,
wherein the first layers have a common first thickness and the second layers have a common second thickness;
selectively removing the second layers of at least the first portion of the superlattice;
exposing the first layers of the at least first portion of the superlattice stack to an etchant and removing a portion of the first material therefrom using second process conditions different than the first process conditions to form trimmed first layers therefrom,
wherein the quantity of material removed from different ones of the first layers are different amounts,
and the quantity of the different amounts is selected based upon at least one of the distance between the capping layers formed on the different ones of the first layers on the first substrate, the thicknesses of the different ones of the capping layers formed on different ones of the trimmed first layers on the first substrate, and the different thicknesses of the combined thickness of different ones of the trimmed first layers and the capping layer formed thereover on the first substrate.
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Colombeau in view of Tanaka as explained above.
With respect to claim 18, Colombeau further teaches:
wherein the space between adjacent layers of the capping material (24) on different trimmed first layers (8’) of the second substrate are equal to one another. (Fig. 12B shows the spaces between the layers of 24, which have a same thickness)
With respect to claim 19, Colombeau further teaches:
wherein the thickness of the capping layer on a layer of the first material closest to the substrate is less than the thickness of the capping layer on a layer of the first material furthest to the substrate. (the process for growing the SiGe cladding layer is described in para. 71 of Colombeau and is similar to the process described in the specification of the instant application. The Examiner takes the position that this limitation is inherent to the deposition process, see Examiner’s note above.)
Claims 7-10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Colombeau (US 2020/0152493 A1) in view of Bhuwalka (US 2017/0256609 A1).
With respect to claim 7, Colombeau teaches:
A method of forming a semiconductor device on a substrate, comprising:
forming a superlattice (6, 8) on the substrate (substrate 2) (para. 55 “A superlattice is formed on the substrate 2. The superlattice includes alternating layers 6, 8 of different materials.”),
the superlattice comprising alternating sub-layers of a first material (8, made of silicon) comprising a semiconductor and sub-layers of a second material (6, made of SiGe) (para. 55 “the alternating layers 6, 8 are silicon germanium (Si.sub.1-xGe.sub.x, where x is in a range from about 0.10 to about 0.40) and silicon, respectively”),
a second sublayer (bottom layer of 8) of the first material interposed between a first sublayer (uppermost layer of 8) of the first material and the substrate (2);
removing the second material sub-layers (6) from the superlattice (see Fig. 10A and 10B);
etching the first sub layer of the first material and the second sublayer of the first material (See Fig. 11A and 11B, trimming process from 8 to 8’),
such that a different quantity of first material is removed from the first sub layer of the first material compared to the amount of material removed from second sublayer of the first material (the trimming process is described by Colombeau is para. 69 and uses a mixture of NF3 and He gas, similar to the process described in the specification of the instant application. The Examiner determines that this limitation is inherent to the etching process as described in the Examiner’s note above);
and depositing a capping layer (cladding layer 24) over the etched first sub layer of the first material (uppermost 8’) and over the etched second sublayer of the first material (lowermost 8’) (para. 70 “The epitaxial growth process forms cladding layers 24 on the trimmed layers 8′ and exposed surfaces of the substrate 2. The cladding layers 24 are on the exposed surfaces of the trimmed layers 8′ and substrate 2”),
wherein the thickness of the capping layer deposited on the first sub layer of the first material is different from the thickness of the capping layer deposited on the second sub layer of the first material (the process for growing the SiGe cladding layer is described in para. 71 of Colombeau and is similar to the process described in the specification of the instant application. The Examiner takes the position that this limitation is inherent to the deposition process, see Examiner’s note above.)
Colombeau fails to teach:
wherein the thicknesses of at least a first sub-layer of the first material layers and a second sub-layer of the first material have different thicknesses,
Bhuwalka teaches in Fig. 5:
wherein the thicknesses of at least a first sub-layer (123) of the first material layers and a second sub-layer (121) of the first material have different thicknesses (para. 55 “the first through third semiconductor layers 121, 122, and 123 may be formed to have first through third thicknesses T1, T2, and T3 in the third direction, respectively. The first through third thicknesses T1, T2, and T3 may change in this order. For example, the first thickness T1 may be greater than the second thickness T2, and the second thickness T2 may be greater than the third thickness T3.”),
Colombeau discloses the claimed invention except for the different thicknesses of the sub-layers. Bhuwalka teaches that it is known to make a GAA device in which the different channels have different thicknesses. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to make a device in which the sublayers that make up the channels have different thicknesses as taught by Bhuwalka, since Bhuwalka states in para. 78 that such a modification would allow for the tuning of current flow through the channels. See MPEP 2144.
With respect to claim 8, Bhuwalka further teaches:
wherein the first sub-layer (121) of the first material is located further from the substrate than the second sublayer (123) of the first material,
and the thickness of the first sub-layer of the first material, prior to being etched,
is greater than the thickness of the second sublayer of the first material,
prior to being etched. (para. 55 “The first through third thicknesses T1, T2, and T3 may change in this order. For example, the first thickness T1 may be greater than the second thickness T2, and the second thickness T2 may be greater than the third thickness T3”)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Colombeau in view of Bhuwalka as explained above.
With respect to claim 9, Colombeau further teaches:
wherein the thickness of the capping layer on the etched first sub-layer of the first material is thicker than the thickness of the capping layer on the etched second sub-layer of the first material. (the process for growing the SiGe cladding layer is described in para. 71 of Colombeau and is similar to the process described in the specification of the instant application. The Examiner takes the position that this limitation is inherent to the deposition process, see Examiner’s note above.)
With respect to claim 10, Colombeau further teaches:
wherein the etched first sub-layer (second from bottom 8’) of the first material has a first side (top) facing away from the second sublayer (bottommost 8’) of the first material and a second side (bottom) facing the second sub-layer of the first material;
the etched second sublayer (bottommost 8’) of the first material has a first side (top) facing the first sub-layer of the first material and a second side (bottom) facing the substrate;
the capping layer (24) is formed at least on the first and second sides of the etched first sub-layer of the first material and at least on the first and second sides of the etched second sub-layer of the first material (24 is formed on both top and bottom, see Fig. 12A-12B);
and the sum of the thickness of the etched first sublayer of the first material and the thicknesses of the capping layer formed on the first and second sides thereof is equal to the sum of the thickness of the etched second sublayer of the first material and the thicknesses of the capping layer formed on the first and second sides thereof. (Colombeau teaches that for all instances of 8 has a thickness in the range of 5 to 10 nm and that the trimming process removes 2 to 3 nm. Fig. 12B shows that the thicknesses are designed to be equal.)
In the event that Colombeau does not teach that the sums of the thicknesses are equal do to inherent limits of the process, which the Examiner does not concede, it would be obvious to tune the etch process parameters to meet the above limitation for the purpose of improving the uniformity of the replacement gate structure, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
With respect to claim 12, Colombeau further teaches:
where the etched first sub-layer of the first material and the etched second sublayer of the first material are silicon layers forming channels in an HGGA device. (para. 17 “The structures formed by such processing can be implemented in, for example, horizontal gate all around field effect transistors (hGAA FETs).”)
Claims 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Colombeau (US 2020/0152493 A1) in view of Bhuwalka (US 2017/0256609 A1) as applied to claim 9 above and further in view of Mochizuki (2023/0065852 A1).
With respect to claim 11, Colombeau further teaches:
wherein the etched first sub-layer (second from bottom 8’) of the first material has a first side (top) facing away from the second sublayer (bottommost 8’) of the first material and a second side (bottom) facing the second sub-layer of the first material;
the etched second sublayer (bottommost 8’) of the first material has a first side (top) facing the first sub-layer of the first material and a second side (bottom) facing the substrate (2);
the capping layer (24) is formed on the first and second sides of the etched first sub-layer of the first material and on the first and second sides of the etched second sub-layer of the first material (24 is formed on both top and bottom, see Fig. 12A-12B);
Colombeau/Bhuwalka fails to teach:
and the distance between the outer surface of the capping layer on the etched first sub-layer of the first material facing the etched second sub-layer of the first material,
and the surface of the capping layer on the etched second sub-layer of the first material facing the etched first sublayer of the first material,
is equal to the spacing between the surface of the capping layer on the etched second sub-layer of the first material facing the substrate and the surface of the capping layer on the substrate furthest from the substrate.
Mochizuki teaches in Fig. 14a-14b:
and the distance between the outer surface of the capping layer (SiGe cladding layer 130 on bottom of 108b) on the etched first sub-layer of the first material facing the etched second sub-layer of the first material,
and the surface of the capping layer (130 on top of 108a) on the etched second sub-layer of the first material facing the etched first sublayer of the first material,
is equal to the spacing between the surface of the capping layer (130 on bottom of 108a) on the etched second sub-layer of the first material facing the substrate and the surface of the capping layer (130 on top of substrate) on the substrate furthest from the substrate. (see Fig. 14a, cladding layer fills in area that was etched leaving the thicknesses equal to the thickness of layers 106a and 106b which have a same thickness as seen in Fig. 9A)
Colombeau/Bhuwalka discloses the claimed invention except for the distances between capping layers being the same. Moshizuki discloses that it is known in the art to provide a gap between adjacent capping layers that is the same for each gap. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the method Colombeau/Bhuwalka with the layer distances of Moshizuki in order to have uniform spaces to form gates in See MPEP 2144 and/or because It has been ruled that changes of thickness are prima facie obvious absent persuasive evidence that the particular size is significant (MPEP 2144.04(IV)(A)).
With respect to claim 13, Colombeau further teaches:
wherein the capping layer comprises silicon germanium (para. 70 “the cladding layers 24 can be silicon germanium”), and the etched first sub-layer of the first material and the capping layer thereover, and the etched second sublayer of the first material and the capping layer thereover, form channels in an HGGA device (para. 17 “The structures formed by such processing can be implemented in, for example, horizontal gate all around field effect transistors (hGAA FETs).”)
Claims 15, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Colombeau (US 2020/0152493 A1) in view of Tanaka (US 2004/0040930 A1) as applied to claim 14 above and further in view of Bhuwalka (US 2017/0256609 A1).
With respect to claim 15, applying the teachings of Tanaka into the method of Colombeau to repeat the manufacturing process based on measurements from a first iteration renders obvious:
further comprising providing a second substrate;
forming a superlattice the second substrate,
selectively removing the second layers of at least the first portion of the superlattice;
exposing the first layers of the at least first portion of the superlattice stack to an etchant and removing a portion of the first material therefrom to form trimmed first layers therefrom.
Colombeau/Tanaka fails to teach:
the superlattice comprising a plurality of alternating first layers composed of a first material and second layers formed of a second material, wherein at least two of the first layers of the superlattice have different thicknesses,
that different thickness selected based at least in part on the differences between at least one of the distance between the capping layers formed on the different ones of the first layers on the first substrate,
the thicknesses of the different ones of the capping layers formed on different ones of the trimmed first layers on the first substrate,
and the different thicknesses of the combined thickness of different ones of the trimmed first layers and the capping layer formed thereover on the first substrate;
selectively removing the second layers of at least the first portion of the superlattice;
exposing the first layers of the at least first portion of the superlattice stack to an etchant and removing a portion of the first material therefrom to form trimmed first layers therefrom.
Bhuwalka teaches:
the superlattice comprising a plurality of alternating first layers composed of a first material and second layers formed of a second material, wherein at least two of the first layers of the superlattice have different thicknesses (para. 55 “the first through third semiconductor layers 121, 122, and 123 may be formed to have first through third thicknesses T1, T2, and T3 in the third direction, respectively. The first through third thicknesses T1, T2, and T3 may change in this order. For example, the first thickness T1 may be greater than the second thickness T2, and the second thickness T2 may be greater than the third thickness T3.”),
It would further be obvious to adjust the starting thickness of the layers that are different thicknesses based on the etch characteristics measured by Tanaka in order to arrive at a desired final thickness, therefore Colombeau/Tanaka/Bhuwalka renders obvious:
that different thickness selected based at least in part on the differences between at least one of the distance between the capping layers formed on the different ones of the first layers on the first substrate,
the thicknesses of the different ones of the capping layers formed on different ones of the trimmed first layers on the first substrate,
and the different thicknesses of the combined thickness of different ones of the trimmed first layers and the capping layer formed thereover on the first substrate;
Colombeau/Tanaka discloses the claimed invention except for the different thicknesses of the sub-layers. Bhuwalka teaches that it is known to make a GAA device in which the different channels have different thicknesses. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to make a device in which the sublayers that make up the channels have different thicknesses as taught by Bhuwalka, since Bhuwalka states in para. 78 that such a modification would allow for the tuning of current flow through the channels. See MPEP 2144. It would have been further obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the thicknesses for a second superlattice based on etching characteristics of the first superlattice to find the optimal starting thicknesses since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
With respect to claim 17, Colombeau further teaches:
wherein the space between adjacent layers of the capping material (24) on different trimmed first layers (8’) of the second substrate are equal to one another. (Fig. 12B shows the spaces between the layers of 24, which have a same thickness)
With respect to claim 20, Colombeau further teaches:
wherein the first layers and the second layers are epitaxial layers (para. 55, “The alternating layers 6, 8 of the superlattice can be formed using any appropriate epitaxial growth process.”)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yeong (US 2024/0014214 A1) currently qualifies as prior art but may be subject to a 102(b)(2) exception and teaches a similar structure in Fig. 8B.
Sirard (Introduction to Plasma Etching, Lam Research, 2017) includes information about plasma etching parameters that can be tuned for an etching process and information about microloading, macroloading, and ARDE that provides additional details about the limitations determined to be inherent.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AARON WAGNER/
Patent Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897