FORMING SHALLOW TRENCH FOR DICING AND STRUCTURES THEREOF

Application No. 18/462,499

• Filed: Sep 07, 2023
• Priority: Jun 09, 2023 — provisional 63/507,150
• Examiner: NGUYEN, THANH T
• Art Unit: 2893
• Tech Center: 2800 — Semiconductors & Electrical Systems
• Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
• OA Round: 1 (Non-Final)

Office Action

Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
The information disclosure statements filed 6/30/26; 1/14/26; 1/30/25 and 10/2/24 have been considered.
Oath/Declaration
Oath/Declaration filed on 9/19/23 has been considered.

Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –

(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.

Claim(s) 1-10, 21-22, 25-30 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JEONG et al. (US Patent Publication No. 2021/0407854).
Referring to figures 1-9F, JEONG et al. teaches a method comprising:
etching a portion of a wafer to form a first trench in a scribe line of the wafer, wherein the scribe line is between a first device die and a second device die of the wafer (101/102), and wherein after the etching, a top surface of the portion of wafer in the scribe line is underlying and exposed to the first trench, and the first trench is between opposing sidewalls of the wafer (see figure 9b);
performing a laser grooving process (see paragraph# 124)) to form a second trench (1356) extending from the top surface further down into the wafer, wherein the second trench is laterally between the opposing sidewalls of the wafer (see figure 9D); and
performing a die-saw process to saw the wafer, wherein the die-saw process is performed from a bottom of the second trench, and wherein the die-saw process results in the first device die to be separated from the second device die (1458, see figure 9E).
Regarding to claim 2, the scribe line has a middle line in middle of the first device die and the second device die, and wherein the first trench crosses the middle line (115, see figures 9E).
Regarding to claim 3, the scribe line comprises a dummy conductive feature (103/104), and wherein the first trench overlaps the dummy conductive feature (see figure 9A).
Regarding to claim 4, the etching is stopped before the dummy conductive feature is exposed (see figure 9B).
Regarding to claim 5, the wafer comprises a top surface dielectric layer (40), and an underlying dielectric layer (20) underlying the top surface dielectric layer, and wherein the etching stops on an additional top surface of the underlying dielectric layer (see figure 9b).
Regarding to claim 6, the die-saw process is performed at a position closer to the first device die than the second device die (see figures 9E-9F, see paragraph# 126-127).
Regarding to claim 7, the first device die comprises a first seal ring (103), and the second device die (104) comprises a second seal ring (104), and wherein the wafer further comprises a test conductive feature (34/70) in the scribe line, and the test conductive feature is between the first seal ring and the first trench (320, see figure 9C).
Regarding to claim 8, wherein at a time when the first trench finishes formation, the scribe line has a single trench therein (see figure 9d).
Regarding to claim 9, the etching is performed through an anisotropic etching process (see figure 9B).
Regarding to claim 10, the second trench formed by the laser grooving process reaches a semiconductor substrate of the wafer (see figure 9d, see paragraph# 125).
Regarding to claim 21, a method comprising:
forming a device die (101/102) comprising: a semiconductor substrate (10);
a seal ring (103/104) over the semiconductor substrate and encircling an active area of the device die (102/101, see figure 9a);
a first dielectric layer (20) over the semiconductor substrate;
a second dielectric layer (40) over the first dielectric layer, wherein the second dielectric layer extends lateral beyond the first dielectric layer; and
a first bond pad (50) in the second dielectric layer (see figure 8), wherein the forming the device die comprises:
etching a wafer, performing a laser grooving on the wafer (see figure 9D), and performing a sawing process on the wafer to separate the device die from a neighboring device die (see figures 9E-9F).
Regarding to claim 22, bonding a package component overlying the device die (101/102), wherein the package component comprises: a second bond pad bonding (120) to the first bond pad (50); and a third dielectric layer (80), wherein the second bond pad (120) is in the third dielectric layer, and wherein the third dielectric layer (80) is bonded to the second dielectric layer (40) of the device die (see figure 9E).
Regarding to claim 25, probing the device die through a test conductive feature (70) outside of the seal ring (104/103), wherein the test conductive feature is in a scribe line between the device die and the neighboring device die (see figure 9B).
Regarding to claim 26, bonding a package component overlying the device die, wherein the test conductive feature is further bonded to an additional bond pad in the package component (see figure 9B).
Regarding to claim 27, the device die comprises a first portion and a second portion outside of, and on opposing sides of the seal ring, wherein the first portion is narrower than the second portion (see figures 9a-9f).
Regarding to claim 28, a method comprising:
forming a wafer comprising a device die (101/102);
singulation the wafer (see figures 9a-9f), so that the device die comprises:
a semiconductor substrate (10), wherein the device die has a first width measured at a first level of the semiconductor substrate (see figure 9b);
a first dielectric layer over the semiconductor substrate, wherein the device die has a second width measured at a second level of the first dielectric layer, and the second width is smaller than the first width (see figure 9d); and
a second dielectric layer over the first dielectric layer, wherein the device die has a third width measured at a third level of the second dielectric layer, and the third width is smaller than the second width (see figure 9F); and
bonding a package component over the device die (see figure 9f, 10).
Regarding to claim 29, each of the first width, the second width, and the third width is measured from a first outmost edge of the device die to an opposing outmost edge of the device die (see figures 9F).
Regarding to claim 30, the device die further comprises: a seal ring (103/104) proximate edges of the device die; and a test conductive feature (70/34) outside of the seal ring, wherein the seal ring is in physical contact with the package component (see figures 9a).
Claim(s) 1-10, 21-30 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by HUANG et al. (US Patent Publication No. 2023/0170258).
Referring to figures 1-21, HUANG et al. teaches a method comprising:
etching a portion of a wafer to form a first trench in a scribe line of the wafer, wherein the scribe line is between a first device die and a second device die of the wafer (111/111*), and wherein after the etching, a top surface of the portion of wafer in the scribe line is underlying and exposed to the first trench, and the first trench is between opposing sidewalls of the wafer (see figure 12);
performing a laser grooving process (1354) to form a second trench (1356) extending from the top surface further down into the wafer, wherein the second trench is laterally between the opposing sidewalls of the wafer (see figure 13); and
performing a die-saw process to saw the wafer, wherein the die-saw process is performed from a bottom of the second trench, and wherein the die-saw process results in the first device die to be separated from the second device die (1458, see figure 14).
Regarding to claim 2, the scribe line has a middle line in middle of the first device die and the second device die, and wherein the first trench crosses the middle line (see figures 12-14).
Regarding to claim 3, the scribe line comprises a dummy conductive feature (352), and wherein the first trench overlaps the dummy conductive feature (see figure 12).
Regarding to claim 4, the etching is stopped before the dummy conductive feature is exposed (see figure 12).
Regarding to claim 5, the wafer comprises a top surface dielectric layer (145), and an underlying dielectric layer (137) underlying the top surface dielectric layer, and wherein the etching stops on an additional top surface of the underlying dielectric layer (see figure 12).
Regarding to claim 6, the die-saw process is performed at a position closer to the first device die than the second device die (see figure 14, see paragraph# 55).
Regarding to claim 7, the first device die comprises a first seal ring (352), and the second device die comprises a second seal ring (352), and wherein the wafer further comprises a test conductive feature in the scribe line, and the test conductive feature is between the first seal ring and the first trench.
Regarding to claim 8, wherein at a time when the first trench finishes formation, the scribe line has a single trench therein (see figure 12).
Regarding to claim 9, the etching is performed through an anisotropic etching process (taper etching, see figure 12).
Regarding to claim 10, the second trench formed by the laser grooving process reaches a semiconductor substrate of the wafer (see figure 13, see paragraph# 53).
Regarding to claim 21, a method comprising:
forming a device die (111) comprising: a semiconductor substrate (104);
a seal ring (352) over the semiconductor substrate and encircling an active area of the device die (129, see figure 3);
a first dielectric layer (135) over the semiconductor substrate;
a second dielectric layer (137) over the first dielectric layer, wherein the second dielectric layer extends lateral beyond the first dielectric layer; and
a first bond pad (141) in the second dielectric layer (see figure 8), wherein the forming the device die comprises:
etching a wafer, performing a laser grooving on the wafer (see figure 13), and performing a sawing process on the wafer to separate the device die from a neighboring device die (see figure 14).
Regarding to claim 22, bonding a package component overlying the device die (111/111*), wherein the package component comprises: a second bond pad bonding (143) to the first bond pad (141); and a third dielectric layer (139), wherein the second bond pad is in the third dielectric layer, and wherein the third dielectric layer (139) is bonded to the second dielectric layer (137) of the device die (see figure 10).
Regarding to claim 23, encapsulating the device die in an encapsulant (145), wherein the encapsulant contacts a top surface of the first dielectric layer to form an interface (see figure 12).
Regarding to claim 24, a first portion of the encapsulant overlaps a second portion of the first dielectric layer (see figure 12).
Regarding to claim 25, probing the device die through a test conductive feature (133) outside of the seal ring (352), wherein the test conductive feature is in a scribe line between the device die and the neighboring device die (see figure 12).
Regarding to claim 26, bonding a package component overlying the device die, wherein the test conductive feature is further bonded to an additional bond pad in the package component (see figure 12).
Regarding to claim 27, the device die comprises a first portion and a second portion outside of, and on opposing sides of the seal ring, wherein the first portion is narrower than the second portion (see figure 12).
Regarding to claim 28, a method comprising:
forming a wafer comprising a device die (111/311);
singulation the wafer (see figures 12-14), so that the device die comprises:
a semiconductor substrate (104), wherein the device die has a first width measured at a first level of the semiconductor substrate (see figure 12);
a first dielectric layer over the semiconductor substrate, wherein the device die has a second width measured at a second level of the first dielectric layer, and the second width is smaller than the first width (see figure 13); and
a second dielectric layer over the first dielectric layer, wherein the device die has a third width measured at a third level of the second dielectric layer, and the third width is smaller than the second width (see figure 14); and
bonding a package component over the device die (see figure 20).
Regarding to claim 29, each of the first width, the second width, and the third width is measured from a first outmost edge of the device die to an opposing outmost edge of the device die (see figures 14, 17).
Regarding to claim 30, the device die further comprises: a seal ring (352) proximate edges of the device die; and a test conductive feature (133) outside of the seal ring, wherein the seal ring is in physical contact with the package component (see figures 14-20).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.

The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over JEONG et al. (US Patent Publication No. 2021/0407854) as applied to claims 1-10, 21-22, 25-30 above, and further in view of Tsai et al. (US Patent Publication No. 2015/0214077).
a method comprising:
forming a device die (101/102) comprising: a semiconductor substrate (10);
a seal ring (103/104) over the semiconductor substrate and encircling an active area of the device die (102/101, see figure 9a);
a first dielectric layer (20) over the semiconductor substrate;
a second dielectric layer (40) over the first dielectric layer, wherein the second dielectric layer extends lateral beyond the first dielectric layer; and
a first bond pad (50) in the second dielectric layer (see figure 8), wherein the forming the device die comprises:
etching a wafer, performing a laser grooving on the wafer (see figure 9D), and performing a sawing process on the wafer to separate the device die from a neighboring device die (see figures 9E-9F).
However, the reference does not clearly teach encapsulating the device die in an encapsulant, wherein the encapsulant contacts a top surface of the first dielectric layer to form an interface, a first portion of the encapsulant overlaps a second portion of the first dielectric layer (in claims 23-24)
Tsai et al. teaches encapsulating the device die in an encapsulant (32), wherein the encapsulant (32) contacts a top surface of the first dielectric layer (24) to form an interface a semiconductive device having a first portion of the encapsulant (32) overlaps a second portion of the first dielectric layer (22, see figure 15).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would form the encapsulant in Jeong et al. as taught by Tsai et al. because the process is known in the semiconductor to protect the device.
The additional references cited in form PTO-892 show further analogous circuitry. Specifically references (He et al. 2023/0178475) are particularly relevant to claimed device and manufacture which recited in claims 1-10, 21-30. He et al. teaches a method of forming semiconductor die. This reference is deemed relevant and should be carefully reviewed before any amendment is filed.

Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is [phone], or by Email via address [e-mail]. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on [phone]. The fax phone number for this Group is [phone].
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893

Prosecution Timeline

• Sep 07, 2023: Application Filed
• Jul 30, 2026: Non-Final Rejection mailed — §102, §103 (current)