DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/13/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment & Claims’ Status
The Amendment filed on 1/9/2026 has been entered. Claims 1-2, 4-11, 13-15, 17-24, and 26-29 are currently pending and being examined. Claims 1-2, 4, 7-11, 13-15, 17, and 20-24 have been amended. Claims 3, 12, 16, and 25 have been cancelled. Claims 26-29 have been newly added. The objections of Claims 9 and 15 are withdrawn due to amendments to the claims addressing the presented informalities of the last Office Action (filed 11/13/2025).
Claim Objections
Claims 1-2, 4-6, 8-11, 13-15, 17-19, 21-24, 27, and 29 are objected to because of the following informalities:
Re Claim 1, line 17 references “an electrical component” which should include a preceding clarifying adjective to differentiate from “a discrete electrical component” in lines 2-3 of Claim 1, such as “an other electrical component” or “a second electrical component”.
Re Claim 8, line 13 references “an electrical component” which should include a preceding clarifying adjective to differentiate from “a first electrical component” in lines 4-5 of Claim 7, such as “a second electrical component”.
Re Claim 13, while Claim 13 is indicated as being dependent on Claim 7, lines 8-9 of Claim 13 reference “the second electrical contact”, which was established in lines 4-5 of Claim 8. The dependence from Claim 7 will be assumed to be a typo, and for or the purposes of examination, Claim 13 will be assumed to be dependent on Claim 8. In relation, line 8 references “a conductive layer” which should include a preceding clarifying adjective to differentiate from “a first conductive layer” in line 9 of Claim 8 and “a second conductive layer” in line 17 of Claim 8, such as “a third conductive layer”.
Re Claim 14, line 19 references “an electrical component” which should include a preceding clarifying adjective to differentiate from “a discrete electrical component” in line 4 of Claim 14, such as “an other electrical component” or “a second electrical component”.
Re Claim 17, this claim is stated as being dependent on Claim 16, which is now cancelled. This dependency is therefore assumed to be a typo, and for the purposes of examination, Claim 17 will be interpreted as being dependent on Claim 14. Additionally, lines 7-8 of Claim 17 include “forming a third conductive layer over the finish as the first electrical contact”, which is assumed to be a typo of “forming a third conductive layer over the finish as the second electrical contact” to be consistent with the steps provided in the Specification.
Re Claims 4, 13, and 17 all reference “a third conductive layer over the finish as the second electrical contact” in their respective final two lines, which contradicts the language of “further including” at the start of each respective claim (as the electrical contacts were already formed/included in respective Claims 1, 7/8, and 14). “a third conductive layer over the finish as the second electrical contact” will instead be interpreted as “wherein the second electrical contact is disposed over the finish”.
Re Claim 21, line 13 references “an electrical component” which should include a preceding clarifying adjective to differentiate from “a first electrical component” in line 4 of Claim 20, such as “a second electrical component”.
Claims 2, 4-6, and 27 inherit the objection to Claim 1, Claims 9-11 inherit the objection to Claim 8, Claims 15, 17-19, and 29 inherit the objection to Claim 14, and Claims 22-24 inherit the objection to Claim 21.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-11, 23-24, 26, and 28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Re Claims 10 and 11, lines 2-3 of both claims reference “the second electrical component” when there was no previously established “a second electrical component”. For the purposes of examination, “the second electrical component” in both Claims 10 and 11 will be interpreted to mean “the electrical component” in reference to “an electrical component” in lines 13-14 of Claim 8.
Re Claims 23 and 24, lines 2-3 of both claims reference “the second electrical component” when there was no previously established “a second electrical component”. For the purposes of examination, “the second electrical component” in both Claims 23 and 24 will be interpreted to mean “the electrical component” in reference to “an electrical component” in line 13 of Claim 21.
Re Claim 26, lines 2-3 reference “the second electrical component” when there was no previously established “a second electrical component”. For the purposes of examination, “the second electrical component” will be interpreted to mean “the electrical component” in reference to “an electrical component” in line 13 of Claim 21 (and Claim 26 will be assumed to be intended to depend from Claim 21, as there is no additional electrical component in Claim 20).
Re Claim 28, lines 2-3 reference “the second electrical component” when there was no previously established “a second electrical component”. For the purposes of examination, “the second electrical component” will be interpreted to mean “the electrical component” in reference to “an electrical component” in lines 13-14 of Claim 8 (and Claim 28 will be assumed to be intended to depend from Claim 8, as there is no additional electrical component in Claim 7).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-11, 13-15, 17-24, and 26-29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Su et al (US 2017/0133351 A1, of record, hereafter Su).
Re Claim 1, Su discloses a semiconductor device (FIG. 8; [0030]-[0032]), comprising:
a pre-molded discrete electrical component (34; [0016]) including a discrete electrical component (40; [0018]) and a first encapsulant (“first encapsulant”, see FIG. Z1 below; [0018], indicated layers together are encapsulating of component 40) deposited over and around the discrete electrical component (40; [0018]) and a first electrical contact (42; [0019]) of the discrete electrical component (40) exposed from the first encapsulant (“first encapsulant”; [0019]);
a second encapsulant (24, 48, 50; [0013]-[0023], layers together are encapsulating of component 34) deposited over and around the pre-molded discrete electrical component (34; [0023]) with a second electrical contact (“second electrical contact”, see FIG. Z1 below; [0024], “vias” connected to “metal traces” of element 52) of the pre-molded discrete electrical component (34) in contact with the first electrical contact (42) of the discrete electrical component (40; [0036], electrical contact) and further in contact with the second encapsulant (24, 48, 50) and exposed from the second encapsulant (24, 48, 50; [0024]);
a first conductive layer (“metal traces” of RDLs 52; [0024]) formed over the second encapsulant (24, 48, 50) and pre-molded discrete electrical component (34; [0024]) and in contact with the second electrical contact (“second electrical contact”) of the pre-molded discrete electrical component (34; [0024]);
an electrical component (58; [0028]) disposed over the first conductive layer (“metal traces” of RDLs 52; [0028]);
a third encapsulant (66, 68; [0029]-[0030], encapsulating elements 56, 58, 70) deposited over the electrical component (58) and first conductive layer (“metal traces” of RDLs 52; [0030]); and
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a second conductive layer (72; [0031]) formed over the third encapsulant (68; [0031]).
FIG. Z1: Annotated version of FIG. 8 of Su
Re Claim 2, Su discloses the semiconductor device according to Claim 1, while further disclosing wherein the device includes a conductive pillar (56; [0026]) formed between the first conductive layer (“metal traces” of RDLs 52) and the second conductive layer (72) through the third encapsulant (66, 68; [0026]).
Re Claim 4, Su discloses the semiconductor device according to Claim 1, while further disclosing wherein the device includes:
a finish (46; [0020]) formed over the first electrical contact (42; [0020]); and
a third conductive layer (“vias” of RDLs 52; [0023]) formed over the finish (46; [0023]) as the second electrical contact (“second electrical contact”; [0024]).
Re Claim 5, Su discloses the semiconductor device according to Claim 1, while further disclosing wherein an interconnect structure (70; [0030]) formed on the electrical component (58; [0030]) is oriented toward the first conductive layer (“metal traces” of RDLs 52; [0030], specifically lowermost layers of RDL 70).
Re Claim 6, Su discloses the semiconductor device according to Claim 1, while further disclosing wherein an interconnect structure (70; [0030]) formed on the electrical component (58; [0030]) is oriented toward the second conductive layer (70; [0030], specifically uppermost layers of RDL 70).
Re Claim 7, Su discloses a semiconductor device (FIG. 8; [0030]-[0032]), comprising:
a semiconductor package (76, excluding 34; [0032]); and
a pre-molded electrical component (34; [0016]) disposed over the semiconductor package (76; [0032], specifically element 24 of 76) including a first electrical component (40; [0018]) and a first encapsulant (“first encapsulant”, see FIG. Z1; [0018], indicated layers together are encapsulating of component 40) deposited over and around the first electrical component (40; [0018]) and a first electrical contact (42; [0019]) of the first electrical component (40) exposed from the first encapsulant (“first encapsulant”; [0019]).
Re Claim 8, Su discloses the semiconductor device according to Claim 7, while further disclosing wherein the semiconductor package (76) includes:
a second encapsulant (24, 48, 50; [0013]-[0023], layers together are encapsulating of component 34) deposited over and around the pre-molded electrical component (34; [0023]) with a second electrical contact (“second electrical contact”, see FIG. Z1; [0024], “vias” connected to “metal traces” of element 52) of the pre-molded electrical component (34) in contact with the first electrical contact (42) of the first electrical component (40; [0036], electrical contact) and further in contact with the second encapsulant (24, 48, 50) and exposed from the second encapsulant (24, 48, 50; [0024]);
a first conductive layer (“metal traces” of RDLs 52; [0024]) formed over the second encapsulant (24, 48, 50) and pre-molded electrical component (34; [0024]) and in contact with the second electrical contact (“second electrical contact”) of the pre-molded electrical component (34; [0024]);
an electrical component (58; [0028]) disposed over the first conductive layer (“metal traces” of RDLs 52; [0028]);
a third encapsulant (66, 68; [0029]-[0030], encapsulating elements 56, 58, 70) deposited over the electrical component (58) and first conductive layer (“metal traces” of RDLs 52; [0030]); and
a second conductive layer (72; [0031]) formed over the third encapsulant (68; [0031]).
Re Claim 9, Su discloses the semiconductor device according to Claim 8, while further disclosing wherein the device includes a conductive pillar (56; [0026]) formed between the first conductive layer (“metal traces” of RDLs 52) and the second conductive layer (72) through the third encapsulant (66, 68; [0026]).
Re Claim 10, Su discloses the semiconductor device according to Claim 8, while further disclosing wherein an interconnect structure (70; [0030]) formed on the second electrical component (58; [0030]) is oriented toward the first conductive layer (“metal traces” of RDLs 52; [0030], specifically lowermost layers of RDL 70).
Re Claim 11, Su discloses the semiconductor device according to Claim 8, while further disclosing wherein an interconnect structure (70; [0030]) formed on the second electrical component (58; [0030]) is oriented toward the second conductive layer (70; [0030], specifically uppermost layers of RDL 70).
Re Claim 13, Su discloses the semiconductor device according to Claim 7, while further disclosing wherein the device includes:
a finish (46; [0020]) formed over the first electrical contact (42; [0020]); and
a conductive layer (“vias” of RDLs 52; [0023]) formed over the finish (46; [0023]) as the second electrical contact (“second electrical contact”; [0024]).
Re Claim 14, Su discloses a method of making a semiconductor device (FIG. 8; [0030]-[0032]), comprising:
providing a pre-molded discrete electrical component (34; [0016]) by,
providing a discrete electrical component (40; [0018]), and
depositing a first encapsulant (“first encapsulant”, see FIG. Z1; [0018], indicated layers together are encapsulating of component 40) over and around the discrete electrical component (40; [0018]) with a first electrical contact (42; [0019]) of the discrete electrical component (40) being exposed from the first encapsulant (“first encapsulant”; [0019]);
depositing a second encapsulant (24, 48, 50; [0013]-[0023], layers together are encapsulating of component 34) deposited over and around the pre-molded discrete electrical component (34; [0023]) with a second electrical contact (“second electrical contact”, see FIG. Z1; [0024], “vias” connected to “metal traces” of element 52) of the pre-molded discrete electrical component (34) in contact with the first electrical contact (42) of the discrete electrical component (40; [0036], electrical contact) and further in contact with the second encapsulant (24, 48, 50) and exposed from the second encapsulant (24, 48, 50; [0024]);
forming a first conductive layer (“metal traces” of RDLs 52; [0024]) formed over the second encapsulant (24, 48, 50) and pre-molded discrete electrical component (34; [0024]) and in contact with the second electrical contact (“second electrical contact”) of the pre-molded discrete electrical component (34; [0024]);
disposing an electrical component (58; [0028]) disposed over the first conductive layer (“metal traces” of RDLs 52; [0028]);
depositing a third encapsulant (66, 68; [0029]-[0030], encapsulating elements 56, 58, 70) deposited over the electrical component (58) and first conductive layer (“metal traces” of RDLs 52; [0030]); and
forming a second conductive layer (72; [0031]) formed over the third encapsulant (68; [0031]).
Re Claim 15, Su discloses the method according to Claim 14, while further disclosing forming a conductive pillar (56; [0026]) between the first conductive layer (“metal traces” of RDLs 52) and the second conductive layer (72) through the third encapsulant (66, 68; [0026]).
Re Claim 17, Su discloses the method according to Claim 14, while further disclosing including:
forming a finish (46; [0020]) formed over the first electrical contact (42; [0020]); and
forming a third conductive layer (“vias” of RDLs 52; [0023]) formed over the finish (46; [0023]) as the second electrical contact (“second electrical contact”; [0024]).
Re Claim 18, Su discloses the method according to Claim 14, while further disclosing including orienting an interconnect structure (70; [0030]) of the electrical component (58; [0030]) toward the first conductive layer (“metal traces” of RDLs 52; [0030], specifically lowermost layers of RDL 70).
Re Claim 19, Su discloses the method according to Claim 14, while further disclosing including orienting an interconnect structure (70; [0030]) of the electrical component (58; [0030]) toward the second conductive layer (70; [0030], specifically uppermost layers of RDL 70).
Re Claim 20, Su discloses a method of making a semiconductor device (FIG. 8; [0030]-[0032]), comprising:
providing a pre-molded electrical component (34; [0016]) by,
providing a first electrical component (40; [0018]), and
depositing a first encapsulant (“first encapsulant”, see FIG. Z1; [0018], indicated layers together are encapsulating of component 40) over and around the first electrical component (40; [0018]) with a first electrical contact (42; [0019]) of the first electrical component (40) being exposed from the first encapsulant (“first encapsulant”; [0019]);
forming a semiconductor package (76, excluding 34; [0032]); and
disposing the pre-molded electrical component (34) over the semiconductor package (76; [0032], specifically element 24 of 76).
Re Claim 21, Su discloses the method according to Claim 20, while further disclosing wherein forming the semiconductor package (76) includes:
depositing a second encapsulant (24, 48, 50; [0013]-[0023], layers together are encapsulating of component 34) deposited over and around the pre-molded electrical component (34; [0023]) with a second electrical contact (“second electrical contact”, see FIG. Z1; [0024], “vias” connected to “metal traces” of element 52) of the pre-molded electrical component (34) in contact with the first electrical contact (42) of the first electrical component (40; [0036], electrical contact) and further in contact with the second encapsulant (24, 48, 50) and exposed from the second encapsulant (24, 48, 50; [0024]);
forming a first conductive layer (“metal traces” of RDLs 52; [0024]) over the second encapsulant (24, 48, 50) and pre-molded electrical component (34; [0024]) and in contact with the second electrical contact (“second electrical contact”) of the pre-molded electrical component (34; [0024]);
disposing an electrical component (58; [0028]) over the first conductive layer (“metal traces” of RDLs 52; [0028]);
depositing a third encapsulant (66, 68; [0029]-[0030], encapsulating elements 56, 58, 70) over the electrical component (58) and first conductive layer (“metal traces” of RDLs 52; [0030]); and
forming a second conductive layer (72; [0031]) over the third encapsulant (68; [0031]).
Re Claim 22, Su discloses the method according to Claim 21, while further disclosing forming a conductive pillar (56; [0026]) between the first conductive layer (“metal traces” of RDLs 52) and the second conductive layer (72) through the third encapsulant (66, 68; [0026]).
Re Claim 23, Su discloses the method according to Claim 21, while further disclosing including orienting an interconnect structure (70; [0030]) of the second electrical component (58; [0030]) toward the first conductive layer (“metal traces” of RDLs 52; [0030], specifically lowermost layers of RDL 70).
Re Claim 24, Su discloses the method according to Claim 21, while further disclosing including orienting an interconnect structure (70; [0030]) of the second electrical component (58; [0030]) toward the second conductive layer (70; [0030], specifically uppermost layers of RDL 70).
Re Claim 26, Su discloses the method according to Claim 20, while further disclosing including an interconnect structure (70; [0030]) formed over the second electrical component (58; [0030]).
Re Claim 27, Su discloses the semiconductor device according to Claim 1, while further disclosing the device includes an interconnect structure (70; [0030]) formed over the electrical component (58; [0030]).
Re Claim 28, Su discloses the semiconductor device according to Claim 7, while further disclosing the device includes an interconnect structure (70; [0030]) formed over the second electrical component (58; [0030]).
Re Claim 29, Su discloses the method according to Claim 14, while further disclosing including an interconnect structure (70; [0030]) formed over the electrical component (58; [0030]).
Response to Arguments
Applicant’s arguments, see Remarks, filed 1/9/2026, with respect to the rejection(s) of claim(s) 1-25 under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a different interpretation of Su under 35 U.S.C. 102(a)(1).
Applicant’s arguments in Remarks (filed 1/9/2026) pg. 1, para. 3 for Claim 1 (similar arguments below are also put forth for Claims 7/8/14/20/21 due to their similar claimed features) that “Su states that metal pillars 44 are electrically coupled to devices 40 so the undefined and unlabeled area must be an interconnect structure, not an encapsulant” are unpersuasive, as there is nothing in the claim language preventing the not directly labeled area (upper layer pointed out as part of the “first encapsulant” in FIG. Z1) from being an interconnect structure AND an encapsulant, in the sense that is an encapsulant (together with layer 36) because it encapsulates element 40. “There is nothing in Su showing a first electrical contact of the discrete electrical component exposed from the first encapsulant” in Remarks (filed 1/9/2026) pg. 2, para. 1 is also unpersuasive, as through-vias 42 are clearly exposed at the bottom surface of substrate 36 (indicated as the lower layer in the “first encapsulant” in FIG. Z1).
Applicant’s arguments in Remarks (filed 1/9/2026) pg. 3, para. 1 that “There is nothing in Su showing a second electrical contact of the pre-molded discrete electrical component in contact with the first electrical contact of the discrete electrical component and further in contact with the second encapsulant and exposed from the second encapsulant” are also unpersuasive, as layers 24, 48, and 50 together encapsulate the pre-molded discrete electrical component 34, and the “second electrical contact”/via indicated in FIG. Z1 is in physical contact with/exposed from layer 50 and electrically connected to layer 42 (see [0036] of Su).
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., in Remarks 1/9/2026 pg. 3, para. 2 for Claim 1 that “the first conductive layer” has “a second electrical contact of the pre-molded discrete electrical component in contact with the first electrical contact of the discrete electrical component and further in contact with the second encapsulant and exposed from the second encapsulant”) are not recited in the rejected claim(s) (only that the second electrical contact exists and has said properties, not that it is part of the first conductive layer). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Regardless, “metal traces” of RDLs 52 (the “first conductive layer”) are both in contact with the vias of RDLs 52 and formed over the second encapsulant (at least over portions 24, 48, and part of 50) and pre-molded discrete electrical component 34.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW N RICHARDS can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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