DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 03/02/2026.
Claims 1-16, and 21-24 are pending in this application.
Applicant made a provisional election without traverse to prosecute the
invention of Group I, claims 1-16, and newly added claims 21-24, is acknowledged.
Claims 17-20 have been cancelled.
Applicant has the right to file a divisional application covering the subject matter of the non-elected claims.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statements (IDS) filed on 09/07/2023, 10/16/2024, and 02/11/2025. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Specification
3. The specification has been checked to the extent necessary to determine the presence of possible minor errors. However, the applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. 112:
(b) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
5. Claim 9 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention.
Claim 9 recites:
“wherein bottom surfaces of the two second source/drain features and a bottom surface of first plurality of nanostructures are coplanar.”
This is unclear of how the bottom surfaces of the two second source/drain features are coplanar with the bottom surface of first plurality of nanostructures, provided that the two second source/drain features sandwich the second plurality of nanostructure, which disposed above the first plurality of nanostructures. The instant drawings, as in figure 9, for example, shows the bottom of the second source/drain features 240-1, 240-2 to be much higher than the bottom surface of the first plurality of nanostructure sandwiched by the first source/drain features 230-1, 230-2. None of the drawings shows the claimed feature of claim 9.
The claim is therefore indefinite.
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
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7. Claims 1-2, and 5-8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie et al. (US 2023/0125316)
Regarding claim 1, Xie discloses a semiconductor structure, comprising:
a semiconductor substrate 10 (see para. 0031, and fig. 18A);
a high-Kappa dielectric layer 12 (para. 0032) disposed on the semiconductor substrate 10;
a first plurality of nanostructures 16NS disposed over the high-Kappa dielectric layer 12;
a middle dielectric layer 28NS and/or 34 disposed over the first plurality of nanostructures 16NS;
a second plurality of nanostructures 16NS over the middle dielectric layer 28NS/34;
a first gate structure 46 wrapping around the first plurality of nanostructures 16NS; and
a second gate structure 46 wrapping around the second plurality of nanostructures 16NS,
wherein the high-Kappa dielectric layer 12 comprises metal nitride, metal oxide, silicon carbide, graphene, or diamond (boron nitride, para. 0032).
Regarding claim 2, Xie discloses the semiconductor structure of claim 1, wherein the metal nitride 12 comprises aluminum nitride or boron nitride. See para. 0032: boron nitride.
Regarding claim 5, Xie discloses the semiconductor structure of claim 1, wherein the first plurality of nanostructures 16N are sandwiched between two first source/drain features 32. See fig. 18A.
Regarding claim 6, Xie discloses the semiconductor structure of claim 5, wherein the two first source/drain features 32 comprise silicon germanium doped with a p-type dopant. See paras. 0059, 0060.
Regarding claim 7, Xie discloses the semiconductor structure of claim 1, wherein the second plurality of nanostructures 16NS are sandwiched between two second source/drain features 36. See fig. 18A.
Regarding claim 8, Xie discloses the semiconductor structure of claim 7, wherein the two second source/drain features comprise silicon doped with an n-type dopant. See paras. 0059, 0060.
8. Claims 1, 3-8, 10, 12, 15, 21, and 24 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Cheng et al. (US 2024/0096946)
Regarding claim 1, Cheng discloses a semiconductor structure, comprising:
a semiconductor substrate 102 (see fig. 2);
a high-Kappa dielectric layer 120 (paras. 0041, 0046) disposed on the semiconductor substrate 102;
a first plurality of nanostructures 112/101 disposed over the high-Kappa dielectric layer 120;
a middle dielectric layer 132 disposed over the first plurality of nanostructures;
a second plurality of nanostructures 112/103 over the middle dielectric layer 132;
a first gate structure 126 wrapping around the first plurality of nanostructures 112; and
a second gate structure 126 wrapping around the second plurality of nanostructures 112,
wherein the high-Kappa dielectric layer 120 comprises metal nitride, metal oxide, silicon carbide, graphene, or diamond (see para. 0046).
Regarding claim 3, Cheng discloses the semiconductor structure of claim 1, wherein the metal oxide comprises yttrium oxide, yttrium aluminum garnet, aluminum oxide, or beryllium oxide. See para. 0046.
Regarding claim 4, Cheng discloses the semiconductor structure of claim 1, wherein the high-Kappa dielectric layer comprises a thickness between about 0.5 nm and about 100 nm. See para. 0046.
Regarding claim 5, Cheng discloses the semiconductor structure of claim 1, wherein the first plurality of nanostructures 112/101 are sandwiched between two first source/drain features 150. See fig. 2.
Regarding claim 6, Cheng discloses the semiconductor structure of claim 5, wherein the two first source/drain features 112 comprise silicon germanium doped with a p-type dopant. See paras. 0025-0027, 0036.
Regarding claim 7, Cheng discloses the semiconductor structure of claim 1, wherein the second plurality of nanostructures 112 are sandwiched between two second source/drain features 154.
Regarding claim 8, Cheng discloses the semiconductor structure of claim 7, wherein the two second source/drain features 154 comprise silicon doped with an n-type dopant. See paras. 0025-0027, 0036. It has been well known that depending on the types of desired transistors for each particular application, the transistors can be doped with various kinds of dopants such as indium, gallium, arsenic, boron, phosphor, etc. This is well known and would involve only routines skills in the art.
Regarding claim 10, Cheng discloses a semiconductor structure, comprising:
a first bottom source/drain feature 150 (see fig. 2) and a second bottom source/drain feature 150 disposed over a substrate 102;
a plurality of bottom channel members 112/101 extending between and in contact with the first bottom source/drain feature 150 and the second bottom source/drain feature 150;
a first bonding layer 132 over the plurality of bottom channel members 112;
a second bonding layer 132 (para. 0046: the insulator forming the middle dielectric layer 132 may include a single layer or may include multiple layers of dielectric material) disposed directly on the first bonding layer 132;
a first top source/drain feature 154 disposed directly over the first bottom source/drain feature 150;
a second top source/drain feature 154 disposed directly over the second bottom source/drain feature 150; and
a plurality of top channel members 112/103 disposed over the second bonding layer 132 and extending between and in contact with the first top source/drain feature 154 and the second top source/drain feature 154,
wherein the first bonding layer 132 and the second bonding layer 132 comprise metal nitride, metal oxide, silicon carbide, graphene, or diamond (para. 0046).
Regarding claim 12, Cheng discloses the semiconductor structure of claim 10, wherein the metal oxide comprises yttrium oxide, yttrium aluminum garnet, aluminum oxide, or beryllium oxide. See para. 0046.
Regarding claim 15, Cheng discloses the semiconductor structure of claim 10, further comprising:
a plurality of inner spacer features 140 interleaving the plurality of bottom channel members 112, wherein the plurality of inner spacer features 140 comprise silicon oxycarbonitride. See para. 0051.
Regarding claim 21, Cheng discloses a semiconductor structure, comprising:
a plurality of bottom channel members 112/101 disposed over a substrate 102 (see fig. 2);
a bottom gate structure 126 wrapping around the plurality of bottom channel members 112/101;
a bottom source/drain feature 150 interfacing with end sidewalls of the plurality of bottom channel members 112;
a first bonding layer 132 over the plurality of bottom channel members 112;
a second bonding layer 132 (para. 0046: the insulator forming the middle dielectric layer 132 may include a single layer or may include multiple layers of dielectric material) disposed over and interfacing the first bonding layer 132;
a plurality of top channel members 112/103 over the second bonding layer 132;
a top gate structure 126 wrapping around the plurality of top channel members 112/103; and
a top source/drain feature 154 interfacing with end sidewalls of the plurality of top channel members 112/103,
wherein the first bonding layer 132 and the second bonding layer 132 comprise metal nitride, metal oxide, silicon carbide, graphene, or diamond (para. 0046).
Regarding claim 24, Cheng discloses the semiconductor structure of claim 21, wherein the bottom source/drain feature 150 comprises silicon germanium (SiGe) and a p-type dopant, wherein the top source/drain feature comprises silicon (Si) and an n-type dopant. See paras. 0025-0027.
Claim Rejections - 35 U.S.C. § 103
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claims 11, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 2024/0096946)
Regarding claim 11, Cheng discloses the semiconductor structure of claim 10, comprising all claimed limitations, as discussed above, and wherein the bonding layers comprising materials such as SiN, SiBCN, SiOCN, AlOx (para. 0046), except for wherein the bonding layers comprising metal nitride, wherein the metal nitride comprises aluminum nitride or boron nitride.
However, it would have been obvious to one of ordinary skills in the art at the time the invention was made that the materials for the bonding layers of Cheng can be chosen from various suitable materials, including SiN, SiBCN, SiOCN, metal oxide such as aluminum oxide (AlOx), and metal nitrides such as aluminum nitride, and boron nitride. It would have been obvious that selecting a known material on the basis of its suitability for the intended use is just within the general skill of a worker in the art.
MPEP § 2144.07 states that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (Claims to a printing ink comprising a solvent having the vapor pressure characteristics of butyl carbitol so that the ink would not dry at room temperature but would dry quickly upon heating were held invalid over a reference teaching a printing ink made with a different solvent that was nonvolatile at room temperature but highly volatile when heated in view of an article which taught the desired boiling point and vapor pressure characteristics of a solvent for printing inks and a catalog teaching the boiling point and vapor pressure characteristics of butyl carbitol; “Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle.” 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a known plastic to make a container of a type made of plastics prior to the invention was held to be obvious); Ryco, Inc. v. Ag-Bag Corp., 857 F.2d 1418, 8 USPQ2d 1323(Fed. Cir. 1988) (Claimed agricultural bagging machine, which differed from a prior art machine only in that the brake means were hydraulically operated rather than mechanically operated, was held to be obvious over the prior art machine in view of references which disclosed hydraulic brakes for performing the same function, albeit in a different environment.). Caterpillar Inc. v. Deere & Co., 224 F.3d 1374, 56USPQ2d 1305 (Fed. Cir. 2000); Al-Site Corp. v. VSI Int ’ l, Inc., 174 F.3d 1308, 1316, 50 USPQ2d 1161, 1165 (Fed. Cir. 1999); Chiuminatta Concrete Concepts, Inc. v. Cardinal Indus. Inc., 145 F.3d 1303, 1309, 46 USPQ2d 1752, 1757 (Fed. Cir. 1998); Lockheed Aircraft Corp. v. United States , 193 USPQ 449, 461 (Ct. Cl. 1977 ); Data Line Corp. v. Micro Technologies, Inc., 813 F.2d 1196, 1 USPQ2d 2052 (Fed. Cir. 1987). In re Leshin, 125 USPQ 416.
See also MPEP § 2183.
Moreover, it is believed that metal oxide such as aluminum oxide (AlOx), and metal nitride such as aluminum nitride, boron nitride are obvious variances of each other in using as bonding layers, and selecting a suitable material for a particular use is within ordinary skills in the art. Should Applicant believe that these are not obvious variance of each other, and that they are patentably distinct, Applicant is required to select a single material for further examination, as required by MPEP.
Regarding claim 16, Cheng discloses the semiconductor structure of claim 10, comprising all claimed limitations, as discussed above, and further wherein the first bottom source/drain feature 150 and the second bottom source/drain feature 150 comprise silicon germanium (paras. 0025-0027, 0036).
Cheng does not particularly teach that wherein the first top source/drain feature and the second top source/drain feature comprise silicon and phosphorus.
However, it would have been obvious and well known to one of ordinary skills in the art at the time the invention was made that depending on the types of desired transistors for each particular application, the transistors can be doped with various kinds of dopants such as indium, gallium, arsenic, boron, phosphor, etc. This is well known and would involve only routines skills in the art.
Allowable Subject Matter
11. Claims 13-14, and 22-23 are allowable.
Claims 13-14 and 22-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed semiconductor structure (in addition to the other limitations in the claim) comprising:
Claims 13-14:
a contact etch stop layer (CESL) disposed over the first bottom source/drain feature; and
a dielectric layer disposed on the CESL,
wherein the CESL is in direct contact with a top surface of the first bottom source/drain feature, a sidewall of the first bonding layer, a sidewall of the second bonding layer, and a bottom surface of the first top source/drain feature.
Claims 22-23:
a bottom contact etch stop layer (CESL) over the bottom source/drain feature; and
a bottom dielectric layer over the bottom CESL, wherein the bottom CESL interfaces with sidewalls of the first bonding layer and the second bonding layer.
Conclusion
12. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 April 27, 2026
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