Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of Species I in the reply filed on 3/1 3 /2026 is acknowledged. Claims 11-12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected Species claims, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/13/2026 . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. 1. Claim(s) 1 -6,8,13-18 is/are rejected under 35 U.S.C. 102 a( 1) as being anticipated by US 20150076557 A1 (Salcedo). Regarding claim 1 , Salcedo shows (Fig. 3C) an electrostatic discharge (ESD) protection circuit, comprising: a silicon controlled rectifier (51+61, para 96) comprising a first well (43 left , para 84) of a first conductivity type (n) in a substrate (49, para 80), and a first doped region (44a, para 90) of a second conductivity type (p) and a first tap region (45d , para 90 ) of the first conductivity type in the first well, the second conductivity type having an opposite polarity to the first conductivity type, wherein the first doped region is coupled to a first pad (2, para 96), and the first tap region is coupled to a second pad (4, para 9 6 ) through a resistor (70, para 96) external to the silicon controlled rectifier. Regarding claim 2 , Salcedo shows (Fig. 3C) wherein the first pad (2) is an input/output pad (IO, para 96) and the second pad (4, Vdd1) is a power pad (para 96) . Regarding claim 3 , Salcedo shows (Fig. 3C) , further comprising a second well (42a, para 97) of the second conductivity type (p) adjacent to the first well (43 left) , and a second tap region (44b, para 90) of the second conductivity type in the second well, wherein the second tap region is coupled to ground (3b, ground or VSS1 or low supply node , para 90) . Regarding claim 4 , Salcedo shows (Fig. 3C) further comprising a second doped region (45a, para 90) of the first conductivity type (n) in the second well (42a , para 97 ) , the second doped region is coupled to ground (3a, ground or VSS1 or second low supply node , para 94) , wherein the first doped region (44a) forms an anode (2 to 44a, para 114, Fig. 6) and the second doped region (45a) forms a cathode (3a to 45a, para 114, Fig. 6) of the silicon controlled rectifier. Regarding claim 5 , Salcedo shows the resistor (70) has a resistance value between about 10k ohms to about 1G ohms (10k, para 9 6 ) . Regarding claim 6 , Salcedo shows wherein the resistor (70) is adjacent to the silicon controlled rectifier and arranged over the substrate (49) . Regarding claim 8 , Salcedo shows wherein the first conductivity type is n-type and the second conductivity type is p-type. Regarding claim 1 3 , Salcedo shows (Fig. 3C) an electrostatic discharge (ESD) protection circuit, comprising: a substrate (49, para 80) ; a silicon controlled rectifier (51+61, para 96) comprising a first well (43 left, para 84) of a first conductivity type (n) in the substrate, and a first doped region (44a, para 90) of a second conductivity type (p) and a first tap region (45d, para 90) of the first conductivity type in the first well, the second conductivity type having an opposite polarity to the first conductivity type, wherein the first doped region is coupled to an input/output pad (2, IO, para 96) ; and an external resistor (70, para 96) adjacent to the silicon controlled rectifier, the resistor is arranged over the substrate, wherein the first tap region is coupled to a power pad (4, VDD1 , para 96 ) through the resistor. Regarding claim 14 , Salcedo shows (Fig. 3C) the resistor (70) has a resistance value between about 10k ohms to about 1G ohms (10k, para 96) . Regarding claim 15 , Salcedo shows (Fig. 3C) further comprising a second well (42a, para 97) of the second conductivity adjacent to the first well (43 left) , a second tap region (44b) of the second conductivity type (p) and a second doped region (45a) of the first conductivity type in the second well, wherein the second tap region and the second doped region are coupled to ground (3a, Vss1 and 3b, Vss1) . Regarding claim 1 6 , Salcedo shows (Fig. 3C) a method of forming a device, comprising: providing a substrate (49, para 80) prepared with a silicon controlled rectifier (para 96), the silicon controlled rectifier including a first well (43 left, para 84) of a first conductivity type (n) in the substrate, and a first doped region (44a, para 90) of a second conductivity type (p) and a first tap region (45d, para 90) of the first conductivity type in the first well; coupling the first doped region to a first pad (2, para 96) ; and coupling the first tap region to a second pad (4, para 94) through a resistor (70, para 96) external to the silicon controlled rectifier. Regarding claim 1 7 , Salcedo shows (Fig. 3C) wherein the first pad is an input/output pad (2, IO, para 96) and the second pad (4, VDD1, para 94) is a power pad. Regarding claim 1 8 , Salcedo shows (Fig. 3C) wherein the resistor (70) is arranged over the substrate (49) . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 1. Claim(s) 7 ,19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Salcedo as applied to claim 1 or 16 above , further in view of US 20140167218 A1 ( Mallikarjunaswamy ) . Regarding claim 7 , Salcedo shows the silicon controlled rectifier , the substrate and the resistor . Salcedo does not show further comprising an isolation region adjacent to the silicon controlled rectifier in the substrate, wherein the resistor is arranged on the isolation region. Mallikarjunaswamy shows (Fig. 6) further comprising an isolation region (255, insulation, para 37) , wherein the resistor (250, resistor made of polysilicon layer, para 37) is arranged on the isolation region. Salcedo in combination with Mallikarjunaswamy teaches the isolation region adjacent to the silicon controlled rectifier in the substrate . It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Mallikarjunaswamy , with resistor on isolation region above SCR, to the invention of Salcedo . The motivation to do so is that the combination produces the predictable result of thermal protection of the SCR from the resistor in operation. Regarding claim 19 , Salcedo shows the silicon controlled rectifier , the substrate and the resistor . Salcedo does not show wherein the substrate comprises an isolation region adjacent to the silicon controlled rectifier in the substrate, and further comprising forming the resistor on the isolation region . Mallikarjunaswamy shows (Fig. 6) wherein the substrate comprises an isolation region (255, insulation, para 37) , and further comprising forming the resistor (250, resistor made of polysilicon layer, para 37) on the isolation region. Salcedo in combination with Mallikarjunaswamy teaches the isolation region adjacent to the silicon controlled rectifier in the substrate . It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Mallikarjunaswamy , with resistor on isolation region above SCR, to the invention of Salcedo. The motivation to do so is that the combination produces the predictable result of thermal protection of the SCR from the resistor in operation. 2. Claim(s) 9 -10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Salcedo as applied to claim 1 above , further in view of US 20110309466 A1 (Nanba) . Regarding claim 9 , Salcedo shows the resistor comprises a layer of resistive material. Salcedo does not show the resistor comprises a silicide block layer on a layer of resistive material. Nanba shows (Fig. 2) the resistor comprises a silicide block layer (17, para 76) on a layer of resistive material (6, para 76) . It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Nanba, with silicide block layer , to the invention of Salcedo. The motivation to do so is that the selection of an art recognized silicide block layer is suitable for the intended use of Salcedo (MPEP §2144.07). Regarding claim 10 , Salcedo as modified with Nanba shows the layer of resistive material comprises polysilicon (Nanba, para 42) . 2. Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Salcedo in view of Mallikarjunaswamy as applied to claim 19 above , further in view of Nanba . Regarding claim 20 , Salcedo in view of Mallikarjunaswamy shows the resistor comprises forming a layer of resistive material on the isolation region . Salcedo in view of Mallikarjunaswamy does not show forming a silicide block layer on the layer of resistive material. Nanba shows (Fig. 2) forming a silicide block layer (17, para 76) on the layer of resistive material (6, para 76) . It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Nanba, with silicide block layer , to the invention of Salcedo. The motivation to do so is that the selection of an art recognized silicide block layer is suitable for the intended use of Salcedo in view of Mallikarjunaswamy (MPEP §2144.07). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT WASIUL HAIDER whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-1554 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 9 a.m. - 6 p.m. . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT William Partridge can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 270-1402 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WASIUL HAIDER/ Primary Examiner, Art Unit 2812