DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Election/Restrictions Applicant’s election without traverse of Invention II, direct to Claims 15-20 in the reply filed on 02/25/2026 is acknowledged and is under consideration.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 09/08/2028 is in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Response to Amendment
The previously presented claims 15-20 have been fully considered for examination based on their merits. New claims 21-34 filed on 02/25/2026 have been fully considered for examination based on their merits. Claims 1-14 are canceled.
Response to Arguments
Applicant elected (see Remarks, pages 7-8, filed 02/25/2026), Invention II, including previously presented (or original) claims, 15-20, and new claims, 21-34, without traverse and are considered and entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15, and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kuo-Cheng Chiang et al, (hereinafter CHIANG), US 20210057525 A1.
Regarding Claim 15, CHIANG teaches a method (Figs. 29, flow chart for a method of forming a GAA-FET device), comprising:
forming (Fig. 29, step 1010) a fin structure (Fig. 2, 102/106, semiconductor fins/semiconductor strip) on a substrate (Fig. 2, 101) that extends along a first lateral direction (annotated Figures 2) of the substrate (Fig. 2, 101), wherein the fin structure (Fig. 2, 102/106, semiconductor fins/semiconductor strip) includes a plurality of alternating first semiconductor layers (Fig. 2, 103) and second semiconductor layers (Fig. 2, 105);
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forming a cap layer (Fig. 4, 113, capping layer) on the fin structure (Figs. 2/4, 102, semiconductor fins);
forming (Fig. 29, step 1030) a dummy gate structure (Fig. 7, 122) over a portion of the fin structure (Figs. 2/7, 102, semiconductor fins), wherein the dummy gate structure (Fig. 7, 122) extends (annotated Figures 7) along the substrate (Figs. 2/7, 101) in a second direction (annotated Figures 7) perpendicular to the first lateral direction (annotated Figure 7), wherein a portion of the cap layer (Fig. 7, 113, capping layer) is between the fin structure (Figs. 2/7, 102, semiconductor fins) and the dummy gate structure (Fig. 7, 122);
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lining sidewalls (Fig. 8, 129S) of the dummy gate structure (Figs. 7/8, 122) with gate spacers (Fig. 8, 129), wherein the gate spacers (Fig. 8, 129) and an adjacent one of the plurality of the first semiconductor layers (Fig. 2, 103) and the second semiconductor layers (Fig. 2, 105) of the fin structure (Figs. 2/8, 102, semiconductor fins) are separated by the cap layer (Figs. 4/8, 113, capping layer);
removing (Fig. 29, step 1080; Fig. 9, the lateral etch recesses both the capping layer, 113, and the first semiconductor layer, 103, [0038]), portions of the fin structure (Figs. 2/9, 102, semiconductor fins) and the cap layer (Fig. 9, 113, capping layer) not underlying the dummy gate structure (Figs. 7-9, 122, an offset “R” between the sidewall, 105S of the second semiconductor layer, 105 and sidewall of the recessed first semiconductor layer, 103, [0038]);
forming source/drain structures (Fig. 11, 133, [0040-0041]) that are respectively coupled to ends of the fin structure (Figs. 2/11, 102/106, semiconductor fins/strips), wherein the source/drain structures (Fig. 11, 133) are formed in locations previously occupied by the portions of the fin structure (Figs. 2/11, 102/106, semiconductor fins/strips) and the cap layer (Fig. 7, 113, capping layer);
removing the dummy gate structure (Fig. 12, 121/123, gate dielectric/gate electrode of the dummy gate structure, 122, are removed in an etching step(s), [0045]) and the underlying cap layer (Fig. 9, 113, capping layer) to form a gate trench (Fig. 13, 128, recesses are formed between the gate spacers, 129, [0045]);
removing the first semiconductor layers (Fig. 29, step 1080; Fig. 9, the lateral etch recesses the first semiconductor layer, 103, [0038]) such that the second semiconductor layers (Fig. 17, 105/110, second semiconductor layer/nanowire) are vertically separated by one another by spaces (annotated Figure 17); and
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forming (Fig. 29, 1030) an active gate structure (Fig. 24, 129/143, gate spacers/gate electrode, [0068]) in the gate trench (Fig. 13, 128, recesses are formed between the gate spacers, 129, [0045]) that wraps around (Fig. 24, 100, GAA-FET device) each of the second semiconductor layers (Figs. 17/23, 105/110, second semiconductor layer/nanowire) of the fin structure (Fig. 24, 106, semiconductor strip) by filling the spaces therebetween (Fig. 23, 131, dielectric material).
Regarding Claim 21, CHIANG teaches a method (Figs. 29, flow chart for a method of forming a GAA-FET device), comprising:
forming (Fig. 29, step 1010) a fin structure (Fig. 2, 102/106, semiconductor fins/semiconductor strip) on a substrate (Fig. 2, 101) that extends along a first lateral direction (annotated Figures 2) of the substrate (Fig. 2, 101), wherein the fin structure (Fig. 2, 102/106, semiconductor fins/semiconductor strip) includes a plurality of alternating first semiconductor layers (Fig. 2, 103) and second semiconductor layers (Fig. 2, 105);
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forming a cap layer (Fig. 4, 113, capping layer) on the fin structure (Figs. 2/4, 102, semiconductor fins);
forming (Fig. 29, step 1030) a dummy gate structure (Fig. 7, 122) over a portion of the fin structure (Figs. 2/7, 102, semiconductor fins), wherein the dummy gate structure (Fig. 7, 122) extends (annotated Figures 7) along the substrate (Figs. 2/7, 101) in a second direction (annotated Figures 7) perpendicular to the first lateral direction (annotated Figure 7), wherein a portion of the cap layer (Fig. 7, 113, capping layer) is between the fin structure (Figs. 2/7, 102, semiconductor fins) and the dummy gate structure (Fig. 7, 122);
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lining sidewalls (Fig. 8, 129S) of the dummy gate structure (Figs. 7/8, 122) with gate spacers (Fig. 8, 129), wherein the gate spacers (Fig. 8, 129) do not contact (annotated Figure 8) an adjacent one of the plurality of semiconductor layers (Fig. 2, 103/105, first/second semiconductor layers) such that a gap dimension is defined therebetween (annotated Figure 8);
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removing (Fig. 29, step 1080; Fig. 9, the lateral etch recesses both the capping layer, 113, and the first semiconductor layer, 103, [0038]), portions of the fin structure (Figs. 2/9, 102, semiconductor fins) not underlying the dummy gate structure (Figs. 7-9, 122, an offset “R” between the sidewall, 105S of the second semiconductor layer, 105 and sidewall of the recessed first semiconductor layer, 103, [0038]);
forming source/drain structures (Fig. 11, 133, [0040-0041]) that are respectively coupled to ends of the fin structure (Figs. 2/11, 102/106, semiconductor fins/strips), wherein the source/drain structures (Fig. 11, 133) are formed in locations previously occupied by the portions of the fin structure (Figs. 2/11, 102/106, semiconductor fins/strips) and the cap layer (Fig. 7, 113, capping layer);
removing the dummy gate structure (Fig. 12, 121/123, gate dielectric/gate electrode of the dummy gate structure, 122, are removed in an etching step(s), [0045]) to form a gate trench (Fig. 13, 128, recesses are formed between the gate spacers, 129, [0045]);
removing the first semiconductor layers (Fig. 29, step 1080; Fig. 9, the lateral etch recesses the first semiconductor layer, 103, [0038]) such that the second semiconductor layers (Fig. 17, 105/110, second semiconductor layer/nanowire) are vertically separated by one another by spaces (annotated Figure 17); and
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forming (Fig. 29, 1030) a gate structure (Fig. 24, 129/143, gate spacers/gate electrode, [0068]) in the gate trench (Fig. 13, 128, recesses are formed between the gate spacers, 129, [0045]) that wraps around (Fig. 24, 100, GAA-FET device) each of the second semiconductor layers (Figs. 17/23, 105/110, second semiconductor layer/nanowire) of the fin structure (Fig. 24, 106, semiconductor strip) by filling the spaces therebetween (Fig. 23, 131, dielectric material), wherein the gap dimension is sufficiently small (annotated Figure 11) such that the gate structure (Figs. 8/24, 122, gate structure; 129/143, gate spacers/gate electrode, [0068]) does not contact (annotated Figure 11) the source/drain structures (Fig. 11, 133).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 17, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHIANG as applied to claim(s) 15, and 21 above, in view of Shahaji B. More et al, (hereinafter MORE), US 20220262955 A1.
Regarding Claim 17, CHIANG teaches the method of claim 15.
CHIANG does not explicitly disclose the method, wherein the gate spacer has a thickness dimension measure along a direction perpendicular to a sidewall of the active gate structure that is 3 nm or greater.
MORE teaches the method (Figs. 1-21C, various stages of manufacturing a semiconductor GAA FET device, [0028]), wherein the gate spacer (Fig. 13A, 65, sidewall spacers. [0054]) has a thickness dimension measure along a direction perpendicular to a sidewall of the active gate structure that is 3 nm or greater (sidewall spacer, 65, has a thickness in a range from about 3 nm to about 20 nm, [0054]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHIANG to incorporate the teachings of MORE, such that the method, wherein the gate spacer has a thickness dimension measure along a direction perpendicular to a sidewall of the active gate structure that is 3 nm or greater, so that as that the transistor dimensions are continually scaled down to sub 10-15 nm technology nodes for the improvements of the GAA FET devices (MORE, [0002]).
Regarding Claim 23, CHIANG teaches the method of claim 21.
CHIANG does not explicitly disclose the method, wherein the gate spacer has a thickness dimension measure along a direction perpendicular to a sidewall of the active gate structure that is 3 nm or greater.
MORE teaches the method (Figs. 1-21C, various stages of manufacturing a semiconductor GAA FET device, [0028]), wherein the gate spacer (Fig. 13A, 65, sidewall spacers. [0054]) has a thickness dimension measure along a direction perpendicular to a sidewall of the active gate structure that is 3 nm or greater (sidewall spacer, 65, has a thickness in a range from about 3 nm to about 20 nm, [0054]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHIANG to incorporate the teachings of MORE, such that the method, wherein the gate spacer has a thickness dimension measure along a direction perpendicular to a sidewall of the active gate structure that is 3 nm or greater, so that as that the transistor dimensions are continually scaled down to sub 10-15 nm technology nodes for the improvements of the GAA FET devices (MORE, [0002]).
Claim(s) 16, 18-20, 22, 24-34 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHIANG as applied to claim(s) 15, 17, 21, and 23 above, and in view of Jaemun Kim et al, (hereinafter KIM), US 20200381251 A1.
Regarding Claim 16, CHIANG teaches the method of claim 15.
CHIANG does not explicitly disclose the method, wherein a gap dimension measured between the gate spacer and the adjacent one of the plurality of the first semiconductor layers and the second semiconductor layers is 0.3 nm or less.
KIM teaches the method (Figs. 2A-2L, method of manufacturing a semiconductor device, [0009]), wherein a gap dimension (annotated Figure 2F) measured between the gate spacer (Fig. 2F, 350) and the adjacent one of the plurality of the first semiconductor layers (Fig. 2F, 210, first semiconductor patterns) and the second semiconductor layers (Fig. 2F, 220, second semiconductor patterns) is 0.3 nm or less (annotated Figure 2F, first thickness, T1 may range from 5Å to about 500Å, [0026]; second thickness T2 less than the first thickness T1, [0067]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHIANG to incorporate the teachings of KIM, such that the method, wherein a gap dimension measured between the gate spacer and the adjacent one of the plurality of the first semiconductor layers and the second semiconductor layers is 0.3 nm or less, so that to prevent the first and second semiconductor patterns (210) and (220) from being oxidized in the process of forming the insulating layer (311) (KIM, [0031]).
Regarding Claim 18, CHIANG teaches the method of claim 15.
CHIANG does not explicitly disclose the method, wherein a portion of the cap layer is disposed between the gate spacer and the adjacent one of the plurality of the second semiconductor layers.
KIM teaches the method (Figs. 2A-2L, method of manufacturing a semiconductor device, [0009]), wherein a portion of the cap layer (Figs. 2D/2E/4C, 300, capping pattern, [0028]) is disposed between the gate spacer (Figs. 2D/2E/4C, 321, sacrificial gate layer; 350, gate spacers) and the adjacent one of the plurality of the second semiconductor layers (Figs. 2D/2E, 220, second semiconductor patterns).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHIANG to incorporate the teachings of KIM, such that a method, wherein a portion of the cap layer is disposed between the gate spacer and the adjacent one of the plurality of the second semiconductor layers, so that, forming an insulating layer on the capping pattern and the top surface of the device isolation pattern, and forming a sacrificial gate pattern intersecting the active pattern on the insulating layer may provide a semiconductor device with improved reliability (KIM, [0004-0006]).
Regarding Claim 19, CHIANG as modified by KIM teaches the method of claim 18.
KIM further teaches the method (Figs. 2A-2L, method of manufacturing a semiconductor device, [0009]), wherein the cap layer (Fig. 2E, 300 capping layer) has a sidewall that forms an angle (annotated Figure 2E) with the adjacent one of the plurality of the first semiconductor layers (Fig. 2E, 210, first semiconductor patterns) and the second semiconductor layers (Fig. 2E, 220, second semiconductor patterns) of between 90 and 100 degrees (annotated Figure 2E).
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Regarding Claim 20, CHIANG as modified by KIM teaches the method of claim 18.
CHIANG further teaches a method (Figs. 29, flow chart for a method of forming a GAA-FET device), wherein an edge of the cap layer (annotated Figure 8, 300, capping pattern) extends from the sidewalls of the gate spacers (Fig. 8, 129/129S) by a dimension measured along a direction perpendicular to the sidewalls (annotated Figure 8) of 2 nm or less ([0026]).
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Regarding Claim 22, CHIANG teaches the method of claim 21.
CHIANG does not explicitly disclose the method, wherein the gap dimension is less than 3 nanometers (nm).
KIM teaches the method (Figs. 2A-2L, method of manufacturing a semiconductor device, [0009]), wherein the gap dimension (annotated Figure 2F) is less than 3 nanometers (nm) (annotated Figure 2F, first thickness, T1 may range from 5Å to about 500Å, [0026]; second thickness T2 less than the first thickness T1, [0067]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHIANG to incorporate the teachings of KIM, such that the method, wherein the gap dimension is less than 3 nanometers (nm), so that to prevent the first and second semiconductor patterns (210) and (220) from being oxidized in the process of forming the insulating layer (311) (KIM, [0031]).
Regarding Claim 24, CHIANG teaches the method of claim 21.
CHIANG does not explicitly disclose the method, wherein the gate spacer and the adjacent one of the plurality of the second semiconductor layers are separated by a cap layer.
KIM teaches the method (Figs. 2A-2L, method of manufacturing a semiconductor device, [0009]), wherein the gate spacer (Figs. 2D/2E/4C, 321, sacrificial gate layer; 350, gate spacers) and the adjacent one of the plurality of the second semiconductor layers (Figs. 2D/2E, 220, second semiconductor patterns) are separated by a cap layer (Figs. 2D/2E/4C, 300, capping pattern, [0028]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHIANG to incorporate the teachings of KIM, such that a method, wherein the gate spacer and the adjacent one of the plurality of the second semiconductor layers are separated by a cap layer, so that, forming an insulating layer on the capping pattern and the top surface of the device isolation pattern, and forming a sacrificial gate pattern intersecting the active pattern on the insulating layer may provide a semiconductor device with improved reliability (KIM, [0004-0006]).
Regarding Claim 25, CHIANG as modified by KIM teaches the method of claim 24.
CHIANG further teaches a method (Figs. 29, flow chart for a method of forming a GAA-FET device), wherein the cap layer (Fig. 8, 300, capping pattern) is formed of silicon germanium ([0026]).
Regarding Claim 26, CHIANG as modified by KIM teaches the method of claim 24.
KIM further teaches the method (Figs. 2A-2L, method of manufacturing a semiconductor device, [0009]), wherein the cap layer (Fig. 2E, 300 capping layer) has a sidewall that forms an angle (annotated Figure 2E) with the adjacent one of the plurality of t semiconductor layers (Fig. 2E, 210/220, first/second semiconductor patterns) of between 90 and 100 degrees (annotated Figure 2E).
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Regarding Claim 27, CHIANG as modified by KIM teaches the method of claim 24.
CHIANG further teaches a method (Figs. 29, flow chart for a method of forming a GAA-FET device), wherein an edge of the cap layer (annotated Figure 8, 300, capping pattern) extends from the sidewalls of the gate spacers (Fig. 8, 129/129S) by a dimension measured along a direction perpendicular to the sidewalls (annotated Figure 8) of 2 nm or less ([0026]).
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Regarding Claim 28, CHIANG teaches a method (Figs. 29, flow chart for a method of forming a GAA-FET device), comprising:
forming (Fig. 29, step 1010) a fin structure (Fig. 2, 102/106, semiconductor fins/semiconductor strip) on a substrate (Fig. 2, 101), wherein the fin structure (Fig. 2, 102/106, semiconductor fins/semiconductor strip) includes a plurality of alternating first semiconductor layers (Fig. 2, 103) and second semiconductor layers (Fig. 2, 105);
forming a cap layer (Fig. 4, 113, capping layer) on the fin structure (Figs. 2/4, 102, semiconductor fins);
forming (Fig. 29, step 1030) a dummy gate structure (Fig. 7, 122) over a portion of the fin structure (Figs. 2/7, 102, semiconductor fins);
lining sidewalls (Fig. 8, 129S) of the dummy gate structure (Figs. 7/8, 122) with gate spacers (Fig. 8, 129), wherein the gate spacers (Fig. 8, 129) and an adjacent one of the plurality of the first semiconductor layers (Fig. 2, 103) and the second semiconductor layers (Fig. 2, 105) of the fin structure (Figs. 2/8, 102, semiconductor fins) are separated by the cap layer (Figs. 4/8, 113, capping layer);
removing the dummy gate structure (Fig. 12, 121/123, gate dielectric/gate electrode of the dummy gate structure, 122, are removed in an etching step(s), [0045]) and the underlying cap layer (Fig. 9, 113, capping layer) to form a gate trench (Fig. 13, 128, recesses are formed between the gate spacers, 129, [0045]) by two or more steps of an etching process ([0045]);
removing the first semiconductor layers (Fig. 29, step 1080; Fig. 9, the lateral etch recesses the first semiconductor layer, 103, [0038]) such that the second semiconductor layers (Fig. 17, 105/110, second semiconductor layer/nanowire) are vertically separated by one another by spaces (annotated Figure 17); and
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forming (Fig. 29, 1030) a gate structure (Figs. 23/24, 129/143, gate spacers/gate electrode, [0068]) in the gate trench (Figs. 13/23, 128, recesses are formed between the gate spacers, 129, [0045]) that has a lower portion (annotated Figure 23) and an upper portion (annotated Figure 23), wherein the lower portion (annotated Figure 23) wraps around (Figs. 23/24, 100, GAA-FET device) each of the second semiconductor layers (Figs. 17/23, 105/110, second semiconductor layer/nanowire) of the fin structure (Fig. 24, 106, semiconductor strip) by filling the spaces therebetween (Fig. 23, 131, dielectric material).
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CHIANG does not explicitly disclose a method, comprising: forming an etch stop layer on the cap layer; wherein portions of the cap layer and the etch stop layer are between the fin structure and the dummy gate structure.
KIM teaches a method (Figs. 2A-2L, method of manufacturing a semiconductor device, [0009]), comprising: forming an etch stop layer (Fig. 2D, 311, insulating layer, may include a semiconductor oxide, for example, silicon oxide, [0028]) on the cap layer (Fig. 2D, 300, capping pattern, [0028]); wherein portions of the cap layer (Fig. 2D, 300, capping pattern, [0028]) and the etch stop layer (Fig. 2D, 311, insulating layer, may include a semiconductor oxide, for example, silicon oxide, [0028]) are between the fin structure (Fig. 2D, 110/200, active pattern) and the dummy gate structure (Fig. 2D, 321, sacrificial gate layer);
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHIANG to incorporate the teachings of KIM, such that a method, comprising: forming an etch stop layer on the cap layer; wherein portions of the cap layer and the etch stop layer are between the fin structure and the dummy gate structure, so that, forming an insulating layer on the capping pattern and the top surface of the device isolation pattern, and forming a sacrificial gate pattern intersecting the active pattern on the insulating layer may provide a semiconductor device with improved reliability (KIM, [0004-0006]).
Regarding Claim 29, CHIANG teaches the method of claim 28.
CHIANG does not explicitly disclose the method, wherein a gap dimension measured between the gate spacer and the adjacent one of the plurality of the first semiconductor layers and the second semiconductor layers is 0.3 nm or less.
KIM teaches the method (Figs. 2A-2L, method of manufacturing a semiconductor device, [0009]), wherein a gap dimension (annotated Figure 2F) measured between the gate spacer (Fig. 2F, 350) and the adjacent one of the plurality of the first semiconductor layers (Fig. 2F, 210, first semiconductor patterns) and the second semiconductor layers (Fig. 2F, 220, second semiconductor patterns) is 0.3 nm or less (annotated Figure 2F, first thickness, T1 may range from 5Å to about 500Å, [0026]; second thickness T2 less than the first thickness T1, [0067]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHIANG to incorporate the teachings of KIM, such that the method, wherein a gap dimension measured between the gate spacer and the adjacent one of the plurality of the first semiconductor layers and the second semiconductor layers is 0.3 nm or less, so that to prevent the first and second semiconductor patterns (210) and (220) from being oxidized in the process of forming the insulating layer (311) (KIM, [0031]).
Regarding Claim 30, CHIANG as modified by KIM teaches the method of claim 28.
CHIANG further teaches a method (Figs. 29, flow chart for a method of forming a GAA-FET device), wherein the etch stop layer (Fig. 12, 135, contact etch stop layer (CESL), [0043]) is formed of silicon monoxide (silicon oxide, [0043]).
KIM further teaches the method (Figs. 2A-2L, method of manufacturing a semiconductor device, [0009]), wherein the etch stop layer (Fig. 2D. 311, insulating layer, [0028]) is formed of silicon monoxide (silicon oxide, [0028]).
Regarding Claim 31, CHIANG as modified by KIM teaches the method of claim 28.
CHIANG further teaches a method (Figs. 29, flow chart for a method of forming a GAA-FET device), wherein the etch stop layer (Fig. 12, 135, contact etch stop layer (CESL), [0043]) is aligned with sidewalls of the gate spacers (Fig. 12, 129, gate spacers, [0045]).
Regarding Claim 32, CHIANG as modified by KIM teaches the method of claim 28.
CHIANG further teaches a method (Figs. 29, flow chart for a method of forming a GAA-FET device), wherein the cap layer (Fig. 8, 300, capping pattern) is formed of silicon germanium ([0026]).
Regarding Claim 33, CHIANG as modified by KIM teaches the method of claim 28.
KIM further teaches the method (Figs. 2A-2L, method of manufacturing a semiconductor device, [0009]), wherein the cap layer (Fig. 2E, 300 capping layer) has a sidewall that forms an angle (annotated Figure 2E) with the adjacent one of the plurality of t semiconductor layers (Fig. 2E, 210/220, first/second semiconductor patterns) of between 90 and 100 degrees (annotated Figure 2E).
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Regarding Claim 34, CHIANG as modified by KIM teaches the method of claim 33.
CHIANG further teaches a method (Figs. 29, flow chart for a method of forming a GAA-FET device), wherein an edge of the cap layer (annotated Figure 8, 300, capping pattern) extends from the sidewalls of the gate spacers (Fig. 8, 129/129S) by a dimension measured along a direction perpendicular to the sidewalls (annotated Figure 8) of 2 nm or less ([0026]).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20220271139 A1 – Figure 17
STATEMENT OF RELEVANCE – The height dimension, H3 may be about 8 nm to about 30 nm, [0039].
US 20220270886 A1 – Figure 1B
STATEMENT OF RELEVANCE – The thickness of the cap layer, 19 is in the range from about 0.5 nm to about 5 nm.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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