Prosecution Insights
Last updated: April 19, 2026
Application No. 18/464,243

DIRECT WRITING SYSTEM USED FOR ELECTRON BEAM LITHOGRAPHY

Non-Final OA §102§103
Filed
Sep 10, 2023
Examiner
CHOI, JAMES J
Art Unit
2878
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
1 (Non-Final)
67%
Grant Probability
Favorable
1-2
OA Rounds
3y 0m
To Grant
99%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allow Rate
250 granted / 374 resolved
-1.2% vs TC avg
Strong +47% interview lift
Without
With
+47.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
63 currently pending
Career history
437
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
63.6%
+23.6% vs TC avg
§102
14.7%
-25.3% vs TC avg
§112
17.8%
-22.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 374 resolved cases

Office Action

§102 §103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of the Application Claim(s) 1-12, 18-25 is/are pending. Claim(s) 1-12, 18-25 is/are rejected. Drawing Objections The drawings are objected to under 37 CFR 1.83(a) because they fail to show the following features as described in the specification. Claim 1 recites “wherein the cavity bottom wall is coplanar with the top surface of the insulator layer” but the drawings (e.g. fig. 1b) appear to show the cavity bottom wall (162) as being coplanar with the insulator layer (132) but not coplanar with either the top surface of the insulator layer (136) nor the bottom surface of the insulator layer (137) (e.g. [0049] of the published application). It is unclear if this is a typographical issue in the claims and/or specification, or a problem with showing the illustrated feature(s) in the drawings. Clarification is respectfully requested. Claims 18 and 21 are objected to for similar reasons as claim 1 above. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as "amended." If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either "Replacement Sheet" or "New Sheet" pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections – 35 U.S.C. § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – PNG media_image1.png 281 1244 media_image1.png Greyscale Claim(s) 1, 2, 7, 18, 21, 22 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Platzgummer et al. (US 20080203317 A1) [hereinafter Platzgummer]. Regarding claim 1, Platzgummer teaches a deflecting plate used for electron beam lithography (EBL), the deflecting plate comprising: a silicon-on-insulator (SOI) substrate (see e.g. claim 17, e.g. fig 8), the SOI substrate comprising: an insulator layer (see e.g. 506) having a top surface and a bottom surface (see fig 8); a device layer (see e.g. 507-510) coupled to the insulator layer at the top surface (see 506), wherein a plurality of deflecting apertures are disposed in the device layer (see fig 8), each of the plurality of deflecting apertures extending from a top open end to a bottom open end in a vertical direction through the device layer (see fig 8, defining as apertures extending down to 506), and wherein the bottom open end is coplanar with the top surface of the insulator layer (see fig 8); and a handle substrate (see e.g. 505) coupled to the insulator layer at the bottom surface (see fig 8), wherein a cavity is disposed in the handle substrate (see fig 8, see also e.g. fig 10), the cavity extending from a cavity open end to a cavity bottom wall (see fig 8), and wherein the cavity bottom wall (defining as bottom wall comprising up to plane of top of insulator layer, 506) is coplanar with the top surface of the insulator layer (see same), such that the bottom open end of each of the plurality of deflecting apertures is exposed to and in spatial connection with the cavity (see fig 8). Regarding claim 2, Platzgummer teaches the plurality of deflecting apertures form a pattern in a horizontal plane (see Platzgummer, claim 1, e.g. fig 11, fig 8, etc). Regarding claim 7, Platzgummer teaches the insulator layer has a thickness from 0.1 μm to 5 μm (see Platzgummer, [0081]). Regarding claim 18, Platzgummer teaches a deflecting plate used for electron beam lithography (EBL), the deflecting plate comprising: a silicon-on-insulator (SOI) substrate (see e.g. claim 17, e.g. fig 8), the SOI substrate comprising: a handle substrate (see e.g. 502); an insulator layer (see e.g. 506) coupled to the handle substrate at a first surface of the insulator layer (see fig 8); and a device layer (see e.g. 507-510) coupled to the insulator layer at a second surface of the insulator layer (see fig 8); a plurality of deflecting apertures (see fig 8) disposed in the device layer (see fig 8), wherein each of the plurality of deflecting apertures extends from a top open end to a bottom open end in a vertical direction through the device layer (see fig 8, defining as apertures extending down to 506), wherein the bottom open end is coplanar with the second surface of the insulator layer (see fig 8), and wherein a plurality of electron beams pass through the plurality of deflecting apertures during an EBL process (see [0062]); and a cavity (see fig 8, see also e.g. fig 10) disposed in the handle substrate, the cavity having a cavity open end, a cavity bottom wall, and a circumferential cavity side wall, wherein the cavity bottom wall (defining as bottom wall comprising up to plane of top of insulator layer, 506) is coplanar with the second surface of the insulator layer, such that the bottom open end of each of the plurality of deflecting apertures is exposed to and in spatial connection with the cavity (see fig 8). Regarding claim 21, Platzgummer teaches a deflecting plate apparatus comprising: a silicon-on-insulator (SOI) substrate (see e.g. claim 17, e.g. fig 8) including a handle substrate (see e.g. 502), an insulator layer (see e.g. 506), and a device layer (see e.g. 507-510); a plurality of deflecting apertures extending vertically through the device layer (see fig 8), wherein a bottom open end of each of the plurality of deflecting apertures (see fig 8, defining as apertures extending down to 506) is coplanar with a top surface of the insulator layer (see fig 8); a plurality of transistors (see e.g. CMOS circuit, 508, [0082]) disposed in the device layer proximate to a front side of the device layer (see fig 8, in close proximity to both sides of device layer; alternately see proximate to 510; alternately defining 507, 508 as device layer), wherein each of the plurality of transistors is electrically connected to components corresponding to one of the plurality of deflecting apertures to control electron deflection (see [0082]); and a cavity (see fig 8, see also e.g. fig 10) extending through the handle substrate to expose the bottom open end of each of the plurality of deflecting apertures (see fig 8). Regarding claim 22, Platzgummer teaches a mask layer (e.g. Platzgummer, fig 8: 509) disposed on the front side of the device layer, wherein the mask layer comprises silicon nitride, silicon oxide (see [0083]), or silicon oxynitride. Claim Rejections – 35 U.S.C. § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: PNG media_image2.png 158 934 media_image2.png Greyscale Claim(s) 3-6, 8-11, 19-20, 24-25 is/are rejected under 35 U.S.C. § 103 as being unpatentable over Platzgummer et al. (US 20080203317 A1) [hereinafter Platzgummer]. Regarding claim 3, Platzgummer teaches a plurality of devices (see e.g. Platzgummer, fig 8: 513) disposed in the device layer (see 507-510), wherein each of the plurality of devices corresponds to one of the plurality of deflecting apertures (see fig 8) and configured to control electron deflection for the corresponding deflecting aperture (see fig 8). Alternately note that although not claimed, it would have been obvious to a person having ordinary skill in the art at the time the application was effectively filed to form the contact component from a plurality of sub parts, including sub parts disposed entirely in the device layer. It is noted it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art. See MPEP 2144.04(V); Nerwin v. Erlichman, 168 USPQ 177, 179. Regarding claim 4, Platzgummer may fail to explicitly disclose each of the plurality of deflecting apertures has a vertical dimension from 45 μm to 55 μm. However, it would have been obvious to a person having ordinary skill in the art at the time the application was effectively filed to adjust the thicknesses of the sublayers that surround the deflecting aperture (e.g. Platzgummer, fig 8, circuit layer 508, protective layers 509, 510) including wherein the composite aperture thickness layer (see e.g. 507-510, 507 may be 2 μm, [0081]) is 45-50 μm, as a routine skill in the art, for example to provide desired circuit structure, provide an optimal amount of protective material to balance protection and cost/complexity, etc. It has held that discovering an optimum or workable ranges involves only routine skill in the art. See In re Aller, 105 USPQ 233. Regarding claim 5, Platzgummer may fail to explicitly disclose the handle substrate has a thickness from 700 μm to 750 μm. However, Platzgummer teaches the handle substrate (see e.g. bulk material, fig 8: 505) allows for dissipating the thermal heat load for the integrated circuits (see [0081]), and provides an example of a thickness being “e.g. 650 μm” (see e.g. [0103]), but it would have been obvious to a person having ordinary skill in the art at the time the application was effectively filed to adjust the thickness of the frame, including a thickness from 700-750 μm, as a routine skill in the art, for example to provide additional thermal heat load capacity, to fit a given outer holding device, and/or as a routine skill in the art to utilize an existing wafer blank. Although the embodiment does not recite the same structure, it would have been obvious to a person having ordinary skill in the art to change the shape as a matter of design choice. See MPEP 2144.04, In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Alternately it is noted the handle substrate may be read on the bulk material and portions of whatever holding structure that is holding the handle substrate in position (see generally fig 1, some kind of holding structure required to hold handle substrate in position). Regarding claim 6, Platzgummer may fail to explicitly disclose the SOI substrate has a total thickness from 750 μm to 800 μm. However, the differences would have been obvious in view of the other teachings of Platzgummer, for similar reasons as claims 4 and/or 5 above. Therefore, the combined teaching of Platzgummer teaches the SOI substrate has a total thickness from 750 μm to 800 μm (based on obvious variations of thicknesses of Platzgummer, 505/706 and/or 508-510). Regarding claim 8, Platzgummer may fail to explicitly disclose the device layer has a total thickness variation (TTV) below 1.5 μm. However, it would have been obvious to a person having ordinary skill in the art at the time the application was effectively filed to try to ensure the layers and coatings are the desired thicknesses as designed (see e.g. Platzgummer, [0081]), thereby minimizing TTV. Although the embodiment does not recite the same structure, it would have been obvious to a person having ordinary skill in the art to change the shape as a matter of design choice. See MPEP 2144.04, In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Regarding claim 9, Platzgummer teaches the insulator layer further comprises: a first insulator layer (see Platzgummer, fig 8: 506) coupled to the handle substrate (see 505); and a second insulator layer (see 506) coupled to the device layer (see 507-510). Platzgummer may fail to explicitly disclose the first and second insulator layers being separated layers and wherein the first insulator layer and the second insulator layer are bonded using fusion bonding. However, the instant claim is a product-by-process claim. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) (citations omitted). See MPEP § 2113. Platzgummer teaches a single merged insulator layer, and under the broadest reasonable interpretation of the claim, there is no evidence that forming or replacing a single insulator layer via fusion bonding of two sub-insulator layers, in at least one portion of the device, would materially affect the structure of the final product. Regarding claim 10, Platzgummer teaches the cavity is defined by the cavity open end, the cavity bottom wall, and a circumferential cavity side wall (see e.g. Platzgummer, fig 8, 10f, note obviousness of selecting partially or fully thinned membrane, e.g. [0104]). Regarding claim 11, Platzgummer teaches wherein the cavity open end (e.g. Platzgummer, fig 8, 10, toward bottom of page) is larger in dimension, in a horizontal plane, than the cavity bottom wall (toward top of page). Claim 19 is rejected for similar reasons as claim 4 above. Regarding claim 20, Platzgummer may fail to explicitly disclose wherein each of the plurality of deflecting apertures has an aspect ratio between 5 and 50. Platzgummer teaches an example where the diameter is 5 μm (see [0107]), but it is unclear if the depth is between 25-250 μm. However, this difference would have been obvious for similar reasons as claim 4 above. Regarding claim 24, Platzgummer teaches the device layer comprises edge regions that are removed (see e.g. Platzgummer, fig 9.15) such that a width of the device layer is less than a width of the handle substrate (see fig 10, [0103]; alternately note obviousness of adjusting thicknesses, for similar reasons as claim 4 above). Claim 25 is rejected for similar reasons as claim 9 above. Claim(s) 12, 23 is/are rejected under 35 U.S.C. § 103 as being unpatentable over Platzgummer, as applied to claim 10 or 21 above, and further in view of Platzgummer (US 20080283767 A1) [hereinafter Platzgummer II]. Regarding claim 12, Platzgummer may fail to explicitly disclose wherein the circumferential cavity side wall defines an angle with respect to the insulator layer, and the angle is between 85 degrees and 120 degrees. It is unclear what the angle in Platzgummer is (see e.g. fig 10, near where reference numeral 706 is printed). However the use of cavity side walls at different angles relative to the aperture plate plane, including at angles between 85-120 degrees, were well known in the art at the time the application was effectively filed. For example, Platzgummer II teaches different angled walls with respect to the aperture surface plane (see e.g. figs 2-8), and It would have been obvious to a person having ordinary skill in the art at the time the application was effectively filed to adjust the angle of the side wall as a routine skill in the art, for example to accommodate different manufacturing methods (wet chemical etching, mechanical milling, other well known wafer thinning methods, etc), while enabling the intended operation of the device. Although the embodiment does not recite the same structure, it would have been obvious to a person having ordinary skill in the art to change the shape as a matter of design choice. See MPEP 2144.04, In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). It is additionally noted that Platzgummer teaches one circumferential cavity side wall (see Platzgummer, fig 8, inside 505) defines an angle with respect to the insulator layer, and the angle is between 85 degrees and 120 degrees (see approximately 90 degrees). Regarding claim 23, Platzgummer teaches the cavity comprises a circumferential cavity side wall that forms an angle greater than 90 degrees with the insulator layer (see Platzgummer, fig 10, [0103-104]). Furthermore, it would have been obvious to a person having ordinary skill in the art at the time the application was effectively filed to adjust the angle of the side wall, for example as a routine skill in the art to enable the intended operation of the system, for similar reasons as discussed in claim 12 above. Although the embodiment does not recite the same structure, it would have been obvious to a person having ordinary skill in the art to change the shape as a matter of design choice. See MPEP 2144.04, In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to James Choi whose telephone number is (571) 272 – 2689. The examiner can normally be reached on 9:30 am – 6:00 pm M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Georgia Epps can be reached on (571) 272 – 2328. The fax phone number for the organization where this application or proceeding is assigned is (571) 273 – 8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAMES CHOI/Examiner, Art Unit 2878
Read full office action

Prosecution Timeline

Sep 10, 2023
Application Filed
Mar 13, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12592360
MULTI CHARGED PARTICLE BEAM WRITING METHOD AND MULTI CHARGED PARTICLE BEAM WRITING APPARATUS
2y 5m to grant Granted Mar 31, 2026
Patent 12586749
CERTAIN IMPROVEMENTS OF MULTI-BEAM GENERATING AND MULTI-BEAM DEFLECTING UNITS
2y 5m to grant Granted Mar 24, 2026
Patent 12555762
Mass Spectrometry Apparatus and Mass Spectrometry Method for Adjusting Ion Accumulation Times Based on Detection Intensity
2y 5m to grant Granted Feb 17, 2026
Patent 12537181
ION TRAP CHIP AND SYSTEM
2y 5m to grant Granted Jan 27, 2026
Patent 12508332
SANITIZING LIGHT ASSEMBLY AND CONVEYOR SYSTEM
2y 5m to grant Granted Dec 30, 2025
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
67%
Grant Probability
99%
With Interview (+47.1%)
3y 0m
Median Time to Grant
Low
PTA Risk
Based on 374 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month