DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 14 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al US 2021/0202332 and further in view of Karnezos US 2006/0284299.
Pertaining to claim 1, Hu teaches the semiconductor package, comprising:
an interposer 102;
at least one semiconductor integrated circuit (IC) die 130 mounted over a first surface of the interposer;
a package substrate 202 bonded to a second surface of the interposer; and
a molding portion 240 contacting the second surface of the interposer 102 and laterally surrounding the package substrate 202 see Figure 2 marked up below.
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Hu fails to teach wherein the molding portion extends at least partially within a space between the package substrate and the second surface of the interposer.
Karnezos teaches a molding portion 207 extending at least partially within a space between a package substrate and a second surface of an interposer See Figure 3 marked up below.
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It would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the molding material encompass the sidewalls and a top portion of a packaged device, the molding between the above mounted interposer and the package substrate. The reason is one of simply feature geometry, not all packages are of the design claimed by Hu, in the alternative, the packaged device could be in the design as taught by Karnezos in Figure 3. This would necessitate the molding material being located as claimed in claim one, simply because space would exist for it to be present. Substituting the package structure shape of Karnezos in Figure 3 with the package structure of Hu, would have been obvious to one of ordinary skill at the time the invention was filed, and would have been done based upon design requirements of the chips presenting themselves in the size/space as taught and show by Karnezos. It would have been within the scope of one of ordinary skill in the art at the time the invention was filed to combine the teachings of Hu and Karnezos to enable the molding step of Hu to be performed according to the teachings of Karnezos because one of ordinary skill in the art at the time the invention was filed would have been motivated to look to alternative suitable methods of performing the disclosed molding step of Hu and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Pertaining to claim 2, Hu teaches the semiconductor package of claim 1, wherein the package substrate comprises a package substrate 201 width dimension that is less than a corresponding interposer 102 width dimension of the interposer See Figure 2 of Hu. See also Figure 3 of Karnezos marked up above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu/Karnezos as applied to claim 1 above.
Pertaining to claims 3 and 9, Hu/Karnezos teaches semiconductor package of claims 1 and 2, wherein the interposer comprises an organic interposer [0002] but is silent on the thickness of the molding portion over a side surface of the package substrate being at least 40 µm and the interposer having a thickness of at least 40 µm. However, It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the thickness of the interposer and thickness of the molding portion through routine experimentation and optimization to obtain optimal or desired device performance because the thickness is a result-effective variable (effects stiffness, warpage, size, cost, function, dielectric protection) and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
Claim(s) 4-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu/Karnezos as applied to claim 1 above, and further in view of Huang et al US 2018/0350755.
Pertaining to claim 4, Hu teaches the semiconductor package of claim 1, wherein a plurality of semiconductor IC dies 130 are mounted over the first surface of the interposer 102 and the molding portion comprises a second molding portion 240, the semiconductor package further comprising:
a first plurality of bonding structures bumps on chips 130 see Figure 2 that bond the plurality of semiconductor IC dies 130 to the first surface of the interposer 102;
Hu/Karnezos fails to teach:
an underfill material portion located between the plurality of semiconductor IC dies and the first surface of the interposer and laterally surrounding the first plurality of bonding structures;
a first molding portion laterally surrounding the plurality of semiconductor IC dies; and
a second plurality of bonding structures that bond the package substrate to the second surface of the interposer,
Huang teaches:
an underfill material portion located between the plurality of semiconductor IC dies and the first surface of the interposer and laterally surrounding the first plurality of bonding structures See Figure 7A marked up below;
a first molding portion 48 laterally surrounding the plurality of semiconductor IC dies; and
a second plurality of bonding structures that bond the package substrate to the second surface of the interposer see Figure 7A marked up below.
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It would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the teachings of Huang into the structure of Hu by including additional molding around the IC chips and substrates and additional bonding structures. The ordinary artisan would have been motivated to modify Hu/Karnezos in the manner set forth above for at least the purpose of protecting further the component devices with a protective encapsulation and protecting the connection points using underfill/molding as taught by Huang.
Pertaining to claim 5, Hu/Karnezos in view of Huang teaches the semiconductor package of claim 4, wherein side surfaces of the semiconductor package are formed by the first molding portion, the interposer, and the second molding portion. Hu in combination with Huang teaches this. The molding 48 around the IC devices of Huang when applied to the structure of Figure 2 in Hu, elements 202, 102 and molding 48 (huang) form the side surface of the semiconductor package.
Pertaining to claim 6, Hu/Karnezos in view of Huang teaches the semiconductor package of claim 5, further comprising at least one of a ring structure and a lid structure mounted to an upper surface of the first molding portion. Huang teaches a lid 70 see Figure7A
Pertaining to claim 7, Hu/Karnezos in view of Huang teaches the semiconductor package of claim 6, wherein the lid structure 70 (Huang) is mounted to the upper surface of the first molding portion 48 and extends over the plurality of semiconductor IC dies 44, and a thermal interface material (TIM) 78 is located between an upper surface of the plurality of semiconductor IC dies and the lid structure See Figure 7A of Huang.
Pertaining to claim 8, Hu/Karnezos in view of Huang teaches the semiconductor package of claim 4, wherein the second plurality of bonding structures comprises solder material portions, and the second molding portion contacts and laterally surrounds the solder material portions See Figure 7A of Huang.
Claim(s) 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu in view of Karnezos and further in view of Huang et al US 2018/0350755.
Pertaining to claim 21, Hu teaches a semiconductor package, comprising:
an interposer 102;
a plurality of semiconductor integrated circuit (IC) dies 130 mounted over a first surface of the interposer;
a package substrate 202 bonded to a second surface of the interposer 102, wherein the package substrate has at least one horizontal dimension that is less than a corresponding horizontal dimension of the interposer See Figure 2;
a second molding portion 240 over the second surface of the interposer and laterally surrounding the package substrate; and
Hu fails to teach:
a first molding portion laterally surrounding the plurality of semiconductor IC dies;
wherein side surfaces of the semiconductor package are formed by the first molding portion, the interposer, and the second molding portion.
Huang teaches:
a first molding portion laterally surrounding the plurality of semiconductor IC dies;
wherein side surfaces of the semiconductor package are formed by the first molding portion, the interposer, and the second molding portion. Hu in combination with Huang teaches this. The molding 48 around the IC devices of Huang when applied to the structure of Figure 2 in Hu, elements 202, 102 and molding 48 (Huang) form the side surface of the semiconductor package.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the teachings of Huang into the structure of Hu by including additional molding around the IC chips and substrates and additional bonding structures. The ordinary artisan would have been motivated to modify Hu in the manner set forth above for at least the purpose of protecting further the component devices with a protective encapsulation as taught by Huang.
Karnevos teaches wherein the second molding portion includes a first segment extending along a side surface of the package substrate and a second segment extending over a surface of the package substrate between the package substrate and the second surface of the interposer.
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It would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the molding material encompass the sidewalls and a top portion of a packaged device, the molding between the above mounted interposer and the package substrate. The reason is one of simply feature geometry, not all packages are of the design claimed by Hu, in the alternative, the packaged device could be in the design as taught by Karnezos in Figure 3. This would necessitate the molding material being located as claimed in claim one, simply because space would exist for it to be present. Substituting the package structure shape of Karnezos in Figure 3 with the package structure of Hu, would have been obvious to one of ordinary skill at the time the invention was filed, and would have been done based upon design requirements of the chips presenting themselves in the size/space as taught and show by Karnezos. It would have been within the scope of one of ordinary skill in the art at the time the invention was filed to combine the teachings of Hu and Karnezos to enable the molding step of Hu to be performed according to the teachings of Karnezos because one of ordinary skill in the art at the time the invention was filed would have been motivated to look to alternative suitable methods of performing the disclosed molding step of Hu and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Pertaining to claim 22, Hu/Karnevos in view of Huang teaches the semiconductor package of claim 21, further comprising an underfill material portion located between the plurality of semiconductor IC dies and the first surface of the interposer. See Figure 7A marked up below
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Pertaining to claim 23, Hu in view of Huang teaches the semiconductor package of claim 21, further comprising at least one of a ring structure and a lid structure 70 (Huang) see Figure 7A mounted to an upper surface of the first molding portion.
Claim(s) 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu/Karnezos as applied to claim 1 above, and further in view of Karpur et al US 2011/0147912.
Pertaining to claims 10 and 11, Hu/Karnezos teaches the semiconductor package of claim 1, but is silent on the type of substrate (Core or coreless) and the thickness. Karpur teaches a semiconductor package substrate that can have a core or be coreless (teaching that these are obvious alternatives to each other) and that the substrate has a thickness from 60 to 1200 microns (less than 1.8mm). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to select based on the teaching of Karpur, a substrate of the claimed characteristic thickness and core type for the purpose of preventing warpage Karpur [0023]
Claim(s) 12, 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu/Karnezos as applied to claim 1 above, and further in view of Wang et al US 2018/0366436.
Pertaining to claim 12, Hu teaches the semiconductor package of claim 1, but fails to teach that the package further comprises a plurality of package substrates bonded to the second surface of the interposer. Wang teaches a semiconductor package with a plurality of package substrates bonded to a second surface of an interposer See Figure 4-6 marked up below. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate more than one package substrate, the ordinary artisan would have been motivated to look to the prior art for the purpose of expanding device functionality by including multiple package substrates.
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Pertaining to claim 14, Hu/Karnezos teaches a semiconductor package, comprising:
an interposer 102 (Huang);
at least one semiconductor integrated circuit (IC) die 130 mounted over a first surface of the interposer 102;
a package substrate 202 bonded to a second surface of the interposer.
Wherein the molding portion extends above surface of the adjacent package substrate that face the second surface of the interposer (taught by Karnezos, see Figure 3)
Hu/Karnezos fails to teach:
a plurality of package substrates, and
a molding portion contacting the second surface of the interposer and located in a gap between adjacent package substrates of the plurality of package substrates.
Wang teaches a semiconductor package with a plurality of package substrates bonded to a second surface of an interposer and a molding portion 133 contact the second surface of the interposer and located in a gap between adjacent package substrates of the plurality of package substrates See Figure 4-6 marked up below. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate more than one package substrate, the ordinary artisan would have been motivated to look to the prior art for the purpose of expanding device functionality by including multiple package substrates.
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Pertaining to claim 15, Hu/Karnezos in view of Wang teaches the semiconductor package of claim 14, wherein the molding portion 133 laterally surrounds each of the package substrates see Figure 4-6 above of Wang, and a thickness of the molding portion between an outer periphery of the plurality of package substrates and a periphery of the interposer is at least 40 µm. It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the thickness of the molding portion through routine experimentation and optimization to obtain optimal or desired device performance because the thickness is a result-effective variable (effects stiffness, warpage, size, cost, function, dielectric protection) and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
With respect to wherein a lateral width of a segment of the molding portion extending over the gap is greater than a lateral width of the gap, this is what would exist of the package of Karnezos was substituted for the packages of Wang, since Figure 3 of Karnezos shows that the width of the molding is larger the closer to the interposer surface compared to adjacent the package substrate, so naturally if two were arranged side by side as in Wang, the lateral width of the molding itself would be larger than the gap between the two adjacent package substrates. See Figure 3 of Karnezos.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu/Karnezos as applied to claim 1 above, and further in view of Jeng et al US 2021/0193637.
Pertaining to claim 13, Hu teaches the semiconductor package of claim 1, but does not teach a package further comprising a functional component bonded to the second surface of the interposer, wherein at least a portion of the functional component is located between the second surface of the interposer and the package substrate. Jeng teaches a functional component 96 located between the second surface of an interposer 20 and a package substrate 102.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the teachings of Jeng into the device of Hu by adding a functional component. The ordinary artisan would have been motivated to modify Hu in the manner set forth above for at least the purpose of expanding functionality and communication of the elements of the package (the functional component of Jeng is a bridge die that facilitates such communication). [0040] see Figure 7
Claim(s) 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu/Karnezos/Wang as applied to claim 14 above, and further in view of Jeng et al US 2021/0193637.
Pertaining to claim 16, Hu in view of Wang teaches the semiconductor package of claim 14, but is silent of the package further comprising a functional component mounted to the second surface of the interposer, wherein the molding portion laterally surrounds the functional component and extends within a gap between the functional component and a package substrate of the plurality of package substrates. Jeng teaches a functional component 96 that is laterally surrounded by a molding 108 and that molding 108 extends within a gap between the component and the package substrate. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the teachings of Jeng into the device of Hu/Wang by adding a functional component. The ordinary artisan would have been motivated to modify Hu in the manner set forth above for at least the purpose of expanding functionality and communication of the elements of the package (the functional component of Jeng is a bridge die that facilitates such communication). [0040] see Figure 7
Pertaining to claim 17, Hu/Wang in view of Jeng teaches the semiconductor package of claim 16, wherein the functional component comprises at least one of a chiplet, an intelligent power device (IPD), and a bridge die. Jeng teaches a bridge die
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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